King Fahd University of Petroleum & Minerals
College of Computer Sciences and Engineering
Computer Engineering Department
Microcomputer System Design COE 305 (3-3-4)
Syllabus
- Instructor: Dr. Mayez Al-Mouhamed (mayez@ccse.kfupm.sa.edu)
- Office: Room 22-325 (Tel. 2934) and Lab 22-339 (Tel. 3536).
- Office hours: S.M.W from 8-9 am and from 10-11 am.
- Text Book: The 80X86 Family: Design, Programming and Interfacing, John Uffenbeck, Prentice-Hall, second edition, 1998.
- Grading:
Exam 1: 15/100,
Exam 2: 15/100 ,
Exam 3: 15/100 ,
Laboratory: 20/100,
Homework: 10/100,
and Final Exam: 25/100 (scheduled by the registrar).
- Attendence: attendence is required by all students.
Excuse for official authorized must be presented to the instructor
no later than one week following the absence.
Unxecused absences lead to a ``DEN'' grade.
Course Objectives: To introduce the fundamental hardware and
software concepts necessary for the design of dedicated microprocessor systems.
Catalog Description:
Microprocessor architecture and organization, Bus architecture, types,
and buffering techniques. Memory and I/O subsystems, organization,
timing, and interfacing. Peripheral controllers and programming.
Practice of the design of a microprocessor system design, testing,
debugging, and reporting.
Prerequisite: COE 200.
Topics covered:
- 1.
- Introduction (4 classes)
Architectural concept, fetch and execute, and cycles.
Programming concept. Introduction to instruction pipelining.
Introduction to memory organization.
Mapping to textbook: the stored program concept,
types of computers,
the 80X86 family of microprocessors (chapter 1),
the 8086 (chapter 3), segmented memory (chapter 3),
and reading on computer operating systems (chapter 2).
- 2.
- Microprocessor model (10 classes)
Microprocessor bus architecture and signals, bus types and
buffering techniques. CPU modes.
Memory and I/O control, bus control, and timings.
Mapping to textbook:
(1) Material from Chapter 6 of first edition of textbook
Reviewing the three-bus system architecture,
basic 8086 CPU hardware module,
generating the 8086 system clock and reset,
microcomputer bus types and buffering techniques, and
the 8086 minimum mode.
(2) Material from Chapter 3 of second edition of textbook
Notion of 80386, the 80486, and Pentium.
- 3.
- Memory subsystem (8 classes)
ROM, PROM, E2PROM, static RAM, and dynamic RAM.
Memory organization and interfacing. Timing and
wait states. Memory controller.
Mapping to textbook: main memory technologies,
(ROM, EPROM E2PROM, SRAM and DRAM),
80X86 processor read/write bus cycles,
80X86 SRAM interface examples, and
address decoding techniques. (Chapter 7).
- 4.
- I/O subsystem (10 classes)
Parallel and serial I/O ports. Programmed I/O,
polling and interrupt-driven I/O.
Interfacing and timing. Interrupt processing and
concurrency resolution. Direct memory access.
Hardware and software Examples.
Mapping to textbook:
Parallel I/O, programmed I/O (chapter 8),
interrupt-driven I/O (chapter 9),
direct memory access (Chapter 9),
serial I/O (chapter 10), and
the EIA RS-232 serial interface,
- 5.
- Peripheral controllers (10 classes)
Polling versus interrupt driven I/O.
the 8255 programmable peripheral interface (PPI) (from chapter 8),
the 8259 programmable interrupt controller (chapter 9),
the PC16550D universal synchronous and asynchronous
receiver/transmitter (chapter 10).
(Programming aspects should be minimized).
- 6.
- Miscellaneous (3 lectures)
notion of mass-storage systems (external sources),
notion of D/A and A/D (external sources),
Notion of personal computer bus systems (chpater 11).
Homework Assignments:
- 1.
- New text book, the following problems from the
Analysis and Design Questions of Chapter 1:
1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, and 1.10.
- 2.
- New text book, the following problems from the
Analysis and Design Questions
of Chapter 3: 3.8, 3.9, 3.10, 3.11, 3.12, 3.13, 3.14, and 3.15.
- 3.
- Old text book, the following problems from the
Analysis and Design Questions
of Chapter 6: 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, and 6.7.
- 4.
- New text book, the following problems from the
Analysis and Design Questions
of Chapter 7: 7.1, 7.2, 7.4, 7.5, 7.7,
7.8, 7.9, 7.10, 7.11, and 7.12.
- 5.
- New text book, the following problems from the
Analysis and Design Questions
of Chapter 8: 8.1, 8.2, 8.3, 8.4, 8.5, 8.6, 8.7, 8.8,
and 8.9.
- 6.
- New text book, the following problems from the
Analysis and Design Questions
of Chapter 9: 9.1, 9.2, 9.3, 9.4, 9.5, 9.6, and 9.8.
Laboratory component
The objective of the lab is to expose the student to
various aspects of microprocessor engineering including
signal analysis, design of medium-sized microprocessor system,
manual wiring, hardware debugging, and getting familiar with a
professional hardware troubleshooting package.
Finally, reporting and documenting on the final product.
Laboratory
(1) Introduction and Review (1 Lab),
(2) TTL and CMOS Tecnology (1 Lab),
(3) Buffering and Latching (1 Lab),
(4) Tools for Timing Analysis (1 Labs),
(5) Timing Analysis of Microprocessors (2 Labs),
(6) Interfacing the Clock Generator to CPU (1 Lab),
(7) Designing a Fully Demultiplexed Bus (2 Labs),
(8) Designing the Memory System (2 Labs),
(9) Preparation for Testing (1 Lab),
(10) Testing of the Microprocessor System (1 Lab),
(11) Interfacing I/O Ports (1 Lab), and
(12) Final Checkup and Project Evaluation (1 Lab).