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COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 202
Course Title: Fundamentals of Computer Engineering
Design: Required Course
Catalog Description
Introduction to Computer Engineering. Digital Circuits. Boolean algebra and switching theory. Manipulation and minimization of Boolean functions. Combinational circuits analysis and design, multiplexers, decoders and adders. Sequential circuit analysis and design, basic flip-flops, clocking and edge-triggering, registers, counters, timing sequences, state assignment and reduction techniques. Register transfer level operations.
Prerequisite(s)
General Physics II (PHYS 102)
Textbook(s) and/or other Required Material
Morris Mano and Charles Kime, Logic and Computer Design Fundamentals, Second Edition, Prentice Hall International, 2000.
Course Objectives
After successfully completing the course, students will be able to
Carry out arithmetic computations in various number systems (Binary, Octal, and Hexadecimal).
Apply rules of Boolean algebra to simplify Boolean expressions.
Translate Boolean expressions into equivalent truth tables and logic gates implementations and vice versa.
Design efficient combinational and sequential logic circuit implementations from functional description of digital systems.
Carry out simple CAD simulations to verify the operation of logic circuits
Topics Covered
Number System and Codes: Information Processing, and representation. Digital vs Analog quantities. General Number Systems. Binary, Octal and Hexadecimal systems. Number System Arithmetic (Addition, Subtraction & Multiplication). Number base conversion. Binary Storage & Registers. Signed Binary Number representation (Signed Mag, Rs &(R-1)s Complement). Signed Binary Addition and Subtraction ((R-1)s, Rs Complement Addition and Subtraction). Codes. BCD, Excess-3, Parity Bits, ASCII & Unicode.
Binary Logic & Gates: Boolean Algebra; basic identities, algebraic manipulation, complement of a function. Canonical and Standard forms, minterms and Maxterms, Sum of products and Products of Sums. Physical properties of gates: fan-in, fan-out, propagation delay, timing diagrams and Tri-state drivers. Map method of simplification: Two-, Three-, Four-and Five-variable K-Maps. Essential prime implicants, simplification procedure, SOP & POS simplification, Dont care conditions. Universal gates; NAND, NOR gates: 2-level implementations. Multilevel Circuits. Exclusive-OR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking.
Combinational Logic: Design Procedure & Examples. Half and Full Adders, Binary Adders: 4-Bit Ripple Carry Adder and delay analysis. Carry Look-Ahead Adder, Adder-Subtractor circuit. MSI parts. Decoders, Decoder expansion, combinational logic implementation using decoders, Encoders & Priority Encoders, Multiplexers, Function Implementation using multiplexers, Demultiplexers, Magnitude Comparator. Design Examples.
Sequential Circuits: Latches, Clocked latches: SR, D, T and JK. Race problem in clocked JK-Latch. Function & Excitation Tables of clocked latches: SR, D, T and JK. Flip-Flops: Master-Slave, and edge-triggered. Function & Excitation Tables of T-FF. Asynchronous/Direct Clear and Set Inputs. Setup &Hold times. Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables. Sequential Circuit Analysis: Input equations, State table. Mealy vs. Moore models of FSMs. Examples. Registers and counters.
Memory & PLDs: Memory devices: RAMs & ROMs . Combinational Circuit Implementation with ROM. Programmable Logic Devices: PLAs, PALs, and FPGAa
Course Contribution to Meet the Professional Component
This course emphasizes the design and analysis of combinational as well as sequential digital logic circuits. For this end, the course also emphasizes the ability of students to use Boolean algebra to simplify functions using both the algebraic and the K-map techniques.
Relationship to Program Outcomes
This course supports the following three program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: Ability to apply math and Boolean algebra in performing computations in various number systems and simplification of Boolean algebraic expressions. [ABET Criterion 3a]
Outcome 2: Ability to design efficient combinational and sequential logic circuit implementations from functional description of digital systems. [ABET Criterion 3c]
Outcome 3: Ability to use CAD tools to simulate and verify logic circuits. [ABET Criterion 3k]
Prepared by: Dr. Alaaeldin Amin, November 19, 2006.
COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 203
Course Title: Digital Logic Laboratory
Design: Required Course
Catalog Description
Review of Digital Logic Design: Design of Combinational Circuits, and Design of Sequential Circuits. Logic implementation using discrete logic components (TTL, CMOS), and programmable logic devices. Introduction to Field Programmable Logic Arrays (FPGAs). The basic design flow: design capture (schematic capture, HDL design entry, design verification and test, implementation (including some of its practical aspects), and debugging. Design of data path and control unit.
Prerequisite(s)
Fundamentals of Computer Engineering (COE 202)
Textbook(s) and/or other Required Material
Morris Mano and Charles Kime, Logic and Computer Design Fundamentals, Third Edition, Prentice Hall International, 2004.
Course Objectives
After successfully completing the course, students will be able to
Design combinational and sequential circuits using discrete components, EEPROMs, and FPGAs to meet certain specifications.
Use basic structural Hardware Description Languages to implement digital circuits.
Design and conduct experiments related to digital systems and analyze their outcomes.
Topics Covered
Combinational Logic Design Review: K-maps, universal gates, and MSI components.
Sequential Logic Design Review: Flip-flops, counters and registers, sequential circuits analysis and design.
Prototyping of logic circuits: Introduction to ICs and discrete components, logic 74xx and 54xx families, power and ground, implementation of a simple combinational circuit.
EEPROM: Introduction to logic prototyping using PLDs, implementation of a sequential circuit using EEPROMs and external registers.
FPGAs and HDL: Introduction to FPGAs design flow, design and implementation of a sequential circuit using schematic design entry, introduction to hardware description languages (HDL), structural modeling using verilog, complete design and implementation of a small combinational circuit, Register Transfer Level (RTL) modeling using verilog, complete design and implementation of a simple datapath, sequential circuit implementation using verilog.
Design and implementation of a data path and control unit: A small processor implementation, integrating HDL and schematic units, data path and control unit design project.
Class/Laboratory Schedule
3 hours per week.
Course Contribution to Meet the Professional Component
This course emphasizes the use of FPGAs and HDL to implement combinational and sequential circuits. The students use various software tools to model, simulate and implement digital circuits. They also design test benches to analyze certain parameters of the circuit. Every week they are required to submit a lab report of the previous experiment. The course project is intended to build the students ability to design, implement, simulate, and verify the operation of a simple datapath and control unit. In the project, the students work in teams. At the end they deliver a presentation and submit a project report.
Relationship to Program Outcomes
This course supports the following five program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: The ability to design combinational and sequential circuits to meet certain specifications [ABET Criterion 3c]
Outcome 2: The ability to use tools and discrete components, EEPROMs, FPGAs, to model, simulate and implement digital circuits. [ABET Criterion 3k]
Outcome 3: The ability to design and conduct experiments related to digital systems and to analyze their outcomes. [ABET Criterion 3b]
Outcome 4: The ability to work in teams. [ABET Criterion 3d]
Outcome 5: The ability to communicate effectively. [ABET Criterion 3g]
Prepared by: Syed Z. Shazli, November 14, 2006.
COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 205
Course Title: Computer Organization & Assembly Language
Design: Required Course
Catalog Description
Introduction to computer organization. Signed and unsigned number representation, character representation, ASCII codes. Assembly language programming, instruction format and types, memory and I/O instructions, dataflow, arithmetic, and flow control instructions, addressing modes, stack operations, and interrupts. Datapath and control unit design. RTL, microprogramming, and hardwired control. Practice of assembly language programming.
Prerequisite(s)
Fundamentals of Computer Engineering (COE 202)
Introduction to Computing I (ICS 102)
Textbook(s) and/or other Required Material
Kip Irvine: Assembly Language for Intel-Based Computers, 4th edition, 2002.
Course Objectives
After successfully completing the course, students will be able to
Describe the basic components of a computer system, its instruction set architecture and its basic fetch-execute cycle operation.
Describe how data is represented in a computer and recognize when overflow occurs.
Recognize the basics of assembly language programming including addressing modes.
Analyze, design, implement, and test assembly language programs.
Recognize, analyze, and design the basic components of a simple CPU including datapath and control unit design alternatives.
Recognize various instruction formats.
Topics Covered
Introduction and Information Representation: Introduction to computer organization. Instruction Set Architecture. Computer Components. Fetch-Execute cycle. Signed number representation ranges. Overflow.
Assembly Language Concepts: Assembly language format. Directives vs. instructions. Constants and variables. I/O. INT 21H. Addressing modes.
Intel x86 Assembly Language Programming: Register set. Memory segmentation. MOV instructions. Arithmetic instructions and flags (ADD, ADC, SUB, SBB, INC, DEC, MUL, IMUL, DIV, IDIV). Compare, Jump and loop (CMP, JMP, Cond. jumps, LOOP). Logic, shift and rotate. Stack operations. Subprograms. Macros. I/O (IN, OUT). String instructions. Interrupts and interrupt processing, INT and IRET.
CPU Design: Register transfer. Data-path design. 1-bus, 2-bus and 3-bus CPU organization. Fetch and execute phases of instruction processing. Performance consideration. Control steps. CPU-Memory interface circuit. Hardwired control unit design. Microprogramming. Horizontal and Vertical microprogramming. Microprogrammed control unit design.
Instruction Set Formats: Fixed vs. variable instruction format. Examples of instruction formats.
Class/Laboratory Schedule
3 lecture hours. Each lecture hour is 50 minutes. The lab is 3 hours per week.
Course Contribution to Meet the Professional Component
This course emphasizes the use of assembly language tools such as the Microsoft Macro Assembler, Linker, and Debugger to develop, analyze, and debug Intel x86 assembly language programs. The lab work emphasizes the use of tools and provides hands on experience in assembly language programming. The course project is intended to make the students apply the concepts learned in the course in designing and implementing a program satisfying a given functionality through team work. The project also involves requirements of self-learning capability.
Relationship to Program Outcomes
This course supports the following five program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: Ability to analyze, design, implement, and test assembly language programs. [ABET Criterion 3c]
Outcome 2: Ability to use tools and skills in analyzing and debugging assembly language programs. [ABET Criterion 3k]
Outcome 3: Ability to design the datapath and control unit of a simple CPU. [ABET Criterion 3c]
Outcome 4: Ability to demonstrate self-learning capability. [ABET Criterion 3i]
Outcome 5: Ability to work in a team. [ABET Criterion 3d]
Prepared by: Dr. Aiman H. El-Maleh, November 12, 2006.
COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 305
Course Title: Microcomputer System Design
Design: Required Course
Catalog Description
Microprocessor architecture and organization, Bus architectures, types and buffering techniques, Memory and I/O subsystems, organization, timing and interfacing, Peripheral controllers and programming. Practice of the design of a microprocessor system design, testing, debugging and reporting.
Prerequisite(s)
Computer Organization and Assembly Language (COE 205)
Textbook(s) and/or other Required Material
Barry B. Brey, The Intel Microprocessors, Processor Architecture, Programming, and Interfacing, Seventh Edition, 2006, Prentice Hall
Course Objectives
After successfully completing the course, students will be able to
Describe the functions of various pins on the processor and processor Memory/IO Read and Write bus cycle operations.
Identify the main types of memory technology, describe memory internal organization and design an interface to memory.
Specify and design simple computer serial and parallel interfaces.
Describe how interrupts are used to implement I/O control and data transfers, design small interrupt service routines and I/O drivers using assembly language.
Describe data access from magnetic and optical disk drives using DMA.
Recognize various types of bus interfaces in a computer system.
Design and fabricate a medium-sized 8086 based microcomputer system.
Topics Covered
80x86 Processor Architecture :Processor Model, Programmers model, Designers Model : 8086 hardware details, Clock generator 8284A, Bus buffering and latching, Processor Read & Write bus cycles, Ready and wait state generation, Coprocessor NDP 8087 interface, 8288 bus controller, Pentium processor architecture.
Memory Interfacing :80x86 processor-Memory interfacing, Address decoding techniques, Memory Devices ROM, EPROM, SRAM, FLASH, DRAM devices, Memory internal organization, Memory read and write timing diagrams, DRAM Controller
Basic I/O Interfacing :Parallel I/O, I/O port address decoding, 8255A PPI programming, Operation modes, Interface examples. Timer Interfacing : 8254 PIT, Timing applications. Serial I/O Interface :Asynchronous communication, EIA RS232 standard, UART 16650, Interface examples.
Interrupts :Interrupt driven I/O, Software & Hardware interrupts, Interrupt processing, 8259A PIC programming, cascading, Interrupt examples.
Direct Memory Access : DMA Controlled I/O, 8237 DMA Controller, Disk Memory Systems- Floppy disk, Hard disk, optical disk memory systems
Bus Interfaces :PC bus standards & interfaces PCI, USB, Firewire, AGP
Class/Laboratory Schedule
3 lecture hours per week. Each lecture hour is 50 minutes. 3 lab hours per week.
Course Contribution to Meet the Professional Component
This course is tightly integrated with a lab component which exposes the student to various aspects of microprocessor engineering including signal analysis, design & fabrication of medium-sized 80x86 microprocessor based system, manual wiring, testing, hardware troubleshooting, and conducting I/O interfacing experiments using professional processor kits.
Relationship to Program Outcomes
This course supports the following seven program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: Ability to apply knowledge of mathematics, probability, and engineering in microprocessor based system design. [ABET Criterion 3a]
Outcome 2: Ability to design and conduct experiments related to microprocessor based system design and to analyze their outcomes. [ABET Criterion 3b]
Outcome 3: Ability to design, debug and test a small scale microprocessor system. [ABET Criterion 3c]
Outcome 4: Ability to function as an effective team member [ABET Criterion 3d]
Outcome 5: Ability to identify, formulate, and solve engineering problems in microprocessor based system design. [ABET Criterion 3e]
Outcome 6: Ability to use design tools for microprocessor system design, test and evaluation. [ABET Criterion 3k]
Outcome 7: Ability to engage in self-learning. [ABET Criterion 3i]
Prepared by: Dr. Abdul Rahim Naseer,
COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 308
Course Title: Computer Architecture
Design: Required Course
Catalog Description
Memory management and cache memory. Integer and floating point arithmetic. Instruction and arithmetic pipelining, superscalar architecture. Reduced Instruction Set Computers. Parallel architectures and interconnection networks.
Prerequisite(s)
Computer Organization and Assembly Language (COE 205)
Textbook(s) and/or other Required Material
David A. Patterson and John L. Hennessy, Computer Organization & Design: The Hardware/Software Interface, 3rd Edition, Morgan Kaufmann, 2005
Course Objectives
After successfully completing the course, students will be able to
Analyze MIPS assembly language code.
Describe and apply integer and floating-point representations and arithmetic.
Compute the execution time, average CPI, and speedup for improvements.
Design the datapath and control logic of simple pipelined/non-pipelined CPUs.
Analyze and compare the performance of different CPU designs.
Analyze the impact of caches and memory organization on performance.
Topics Covered
Instruction set architecture versus Organization, Components, Abstraction, Technology trends, Chip manufacturing process.
Instruction set design, Instruction formats, Addressing modes, CISC versus RISC, Writing MIPS assembly language code.
CPU performance and metrics, CPI, MIPS as a metric, Amdahl's law, Benchmarks, Performance of recent processors.
Computer arithmetic, Integer multiplication and division, Floating-point and IEEE 754 standard, Floating-point addition and multiplication, Rounding.
Processor design, Register transfer, Datapath components, Clocking, Single cycle and multicycle datapath, Control signals, Control unit, Performance.
Instruction pipelining, MIPS 5-stage pipelined datapath, Control, Performance, Hazards, Stall and forwarding, Compiler scheduling, Branch prediction.
Memory hierarchy, DRAM and SRAM, Locality, Cache memory organization, Cache misses, Write policy, Block replacement, Cache performance.
Virtual memory, Page tables and TLB, Virtual/physical caches.
I/O subsystem and devices, Disk operation and performance, RAID, Buses, Bus operation, DMA, I/O performance.
Introduction to multiprocessors, Shared-memory, Cache coherence, Message-passing, Interconnection networks.
Class/Laboratory Schedule
3 lecture hours per week. Each lecture hour is 50 minutes.
Course Contribution to Meet the Professional Component
This course emphasizes the use of MIPS assembly language tools such as the SPIM and MARS software simulators to develop, analyze, and debug MIPS assembly language programs. It also emphasizes the use of simulators for the design and the simulation of the datapath and control of a processor. The course project is intended to build the students ability to design, implement, simulate, and test the operation of a simple pipelined processor.
Relationship to Program Outcomes
This course supports the following five program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: Ability to apply knowledge of mathematics, probability, and statistics in computer performance evaluation. [ABET Criterion 3a and 3L]
Outcome 2: Ability to design the datapath and control of a processor. [ABET Criterion 3c]
Outcome 3: Ability to identify, formulate, and solve computer architecture problems. [ABET Criterion 3e]
Outcome 4: Ability to use simulator tools. [ABET Criterion 3k]
Outcome 5: Ability to engage in self-learning. [ABET Criterion 3i]
Prepared by: Dr. Muhamed F. Mudawar, November 7, 2006.
COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 341
Course Title: Data and Computer Communications
Design: Required Course
Catalog Description
Introduction to data communication. Overview of the OSI model. Frequency response, bandwidth, filtering and noise. Fourier series and Fourier transform. Information theory concepts: Nyquist's theorem, Shannon's and Sampling theorems. Analog and digital modulation techniques. Pulse Code Modulation (PCM). Communication systems circuits and devices. Data encoding. Physical layer protocols. Data link control (point to point communication, design issues, link management, error control, flow control). Multiplexing and switching.
Corequisite
Probability and Statistics for Engineers and Scientists (STAT 319)
Textbook(s) and/or other Required Material
Data and Computer Communication, William Stalling, Prentice Hall International, 7th Edition, 2004.
Course Objectives
After successfully completing the course, students will be able to:
Appreciate the importance of data communication standards, protocols, and protocol architectures.
Describe fundamental concepts in communications, including signal spectrum, power spectral density, effective bandwidth, filtering, signal to noise ratio, channel capacity, and error rate.
Compare and contrast various types of transmission media for both guided and guided propagation regarding cost, transmission impairments and applications.
Identify trade offs governing the choice of analog/digital and synchronous/asynchronous transmission techniques and different signal encoding and modulation schemes.
Analyze and design simple communication links using guided and unguided media, hardware for generating CRC error detection codes and performing error detection, HDLC flow and error control mechanisms, and basic PCM and Delta modulation systems.
Compare and contrast different multiplexing techniques, e.g. FDM, WDM, TDM, and statistical TDM.
Topics Covered
Communication and Networking Models: Communication Model, Data Communications, Networking. Protocols (characteristics and functions) and Protocol Architecture (The OSI model).
Data Transmission: Concepts and terminology, Analog and Digital Data Transmission, Fourier Series Analysis and Fourier Transform Representation, Transmission Impairments, Nyquist and Shannon channel capacities.
Guided and Wireless Transmission: Guided transmission media, Wireless transmission.
Signal Encoding Techniques: Digital Data Digital Signals, Digital Data Analog Signals, Analog Data - Digital Signals, Analog Data Analog Signal.
Digital Data Communication Techniques: Asynchronous and synchronous data interface, Error types, Error Detection, Flow Control and Error Control (stop-and-wait and sliding window). HDLC frames and control mechanisms.
Multiplexing: Frequency division multiplexing, Time division multiplexing (synchronous and statistical), Asymmetric digital subscriber line (ASDL).
Class/Laboratory Schedule
3 lecture hours per week. Each lecture hour is 50 minutes.
Course Contribution to Meet the Professional Component
This course includes a programming assignment where students use software tools to develop skills for the simulation, analysis, and design of communication processes and components. A term paper assignment gives students exposure to recent developments in the field and enhances their aptitudes for research and self-learning.
Relationship to Program Outcomes
This course supports the following five program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: Ability to apply knowledge of mathematics to establish basic concepts in communication engineering. [ABET Criterion 3a]
Outcome 2: Ability to analyze and design communication systems, processes, and components. [ABET Criterion 3c]
Outcome 3: Ability to identify, formulate, analyze, and solve communication engineering problems. [ABET Criterion 3e]
Outcome 4: Ability to use programming tools and skills for the simulation, analysis, and design of communication systems and components. [ABET Criterion 3k]
Outcome 5: Ability to demonstrate self learning skills and aptitudes. [ABET Criterion 3i]
Prepared by: Dr. Radwan E. Abdel-Aal, November 7, 2006.
COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 344
Course Title: Computer Networks
Design: Required Course
Catalog Description
This course will be taught using the top-down approach. Topics covered include introduction to computer networks, OSI model, WAN and LAN design issues. Application layer design issues and protocols are discussed. Then, Transport layer design issues, protocols as well as congestion control mechanisms are presented. Socket programming is explained. An in-depth analysis is presented of the Network layer design issues, and internetworking. MAC layer design issues and protocols are presented.
Prerequisite(s)
Data and Computer Communications (COE 341)
Textbook(s) and/or other Required Material
J. Kurose & K. Ross, Computer Networking: A Top-Down Approach Featuring the Internet, 3rd Edition, Addison Wesley, 2005
Course Objectives
After successfully completing the course, students will be able to
Apply knowledge of mathematics, probability, and statistics to model and analyze some networking protocols.
Design, implement, and analyze simple computer networks.
Identify, formulate, and solve network engineering problems.
Use techniques, skills, and modern networking tools necessary for engineering practice.
Topics Covered
Introduction: What is the Internet, What is a protocol?, Network Edge, Network Core, Network Access, Physical Media, Delay and Loss in Packet-Switched Networks, Protocol Layers and their Service Models, Internet Backbones, NAPs and ISPs, Brief History of Computer Networking and the Internet.
Application Layer: Principles of Application Layer Protocols, HTTP, FTP, Electronic Mail in the Internet, DNS, P2P File Sharing.
Transport Layer: Services and Principles, Multiplexing and Demultiplexing Applications, UDP, Principles of Reliable of Data Transfer: TCP case study, Principles of Congestion Control.
Network Layer: Service Models, What is Inside a Router?, IP: the Internet Protocol, Routing Algorithms, Hierarchical Routing, Routing in the Internet.
Link Layer & LANs: Link Layer: Services, Multiple Access Protocols and LANs, LAN Addresses and ARP, Ethernet, Hubs, Bridges and Switches, PPP.
Wireless & Mobile Networks: Wireless Links & Network Characteristics, CDMA, Wireless LANs: IEEE 802.11, WPAN & Bluetooth, Introduction to mobile networking.
Class/Laboratory Schedule
3 lecture hours and 3 laboratory hours per week. Each lecture hour is 50 minutes.
Course Contribution to Meet the Professional Component
This course lays the ground for subsequent courses in the program on networking. It includes a laboratory where students use software and hardware tools to develop skills for the design, implementation, and analysis of computer networks.
Relationship to Program Outcomes
This course supports the following five program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: Ability to apply knowledge of mathematics, probability, and statistics to model and analyze some networking protocols. [ABET Criterion 3a]
Outcome 2: Ability to design, implement, and analyze simple computer networks. [ABET Criterion 3b]
Outcome 3: Ability to identify, formulate, and solve network engineering problems. [ABET Criterion 3e]
Outcome 4: Knowledge of contemporary issues in computer networks. [ABET Criterion 3j]
Outcome 5: Ability to use techniques, skills, and modern networking tools necessary for engineering practice. [ABET Criterion 3k]
Prepared by: Dr. Marwan H. Abu-Amara, November 11, 2006.
COURSE SYLLABUS
Department, Number and Course Title
Department: Computer Engineering
Course Number: COE 360
Course Title: Principles of VLSI Design
Design: Required Course
Catalog Description
MOS Transistor operation and limitations, MOS digital logic circuits (NMOS & CMOS), static & dynamic logic, combinational and sequential circuits, propagation delay, transistor sizing, MOS IC fabrication, layout and design rules, stick diagrams, IC Design and Verification Tools, subsystem design and case studies, and practical considerations.
Prerequisite(s)
Electronics I (EE 203)
Textbook(s) and/or other Required Material
S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, 2nd ed., 1999. Also some handouts on various topics will be used inshaAlla.
Course Objectives
After successfully completing the course, students will be able to
Apply knowledge of mathematics, science, and engineering in the design, analysis and modeling of digital integrated circuits.
Design and conduct experiments using SPICE to characterize and optimize digital integrated circuits.
Design, Verify, Analyze and Evaluate the performance (speed, Power, Area, Noise margins) of different MOS digital integrated circuits for different design specifications.
Use various CAD tools in the design and verification of digital integrated circuits.
Function as an effective team member in digital integrated circuits design projects.
Document and communicate the design efforts effectively using written reports.
Topics Covered
Review of basic semiconductors properties
Structure, behavior and modeling of PN-junctions (Diodes)
Structure, behavior and modeling of Metal-Oxide-Semiconductor Transistors (MOSFETs)
Scaling and scaling effects of MOS transistors
Design of digital MOS Circuits; NMOS inverter, CMOS inverter, CMOS logic gates, CMOS sequential circuits
Modeling and Simulation of CMOS integrated circuits with SPICE
CMOS Processing Technology and Fabrication
CMOS design rules and layout techniques, floor planning, and parasitics
CMOS IC Design, Design styles and Case Studies
Class/Laboratory Schedule
3 lecture hours per week. Each lecture hour is 50 minutes.
Course Contribution to Meet the Professional Component
This course emphasizes the use of CAD tools for the design and verification of digital integrated circuits. The course project is intended to build the students ability to design, and verify a digital integrated circuit. It also helps developing the students ability to plan, work within a team and to communicate his design efforts.
Relationship to Program Outcomes
This course supports the following five program outcomes out of the outcomes required by ABET Criterion 3 for accrediting computer engineering programs.
Outcome 1: Ability to apply knowledge of mathematics, science, and engineering in the design, analysis and modeling of digital integrated circuits [ABET Criterion 3a]
Outcome 2: Ability to design and conduct experiments using SPICE to characterize and optimize digital integrated circuits [ABET Criterion 3b]
Outcome 3: Ability to Design, Verify, Analyze and Evaluate the performance (speed, Power, Area, Noise margins) of different MOS digital integrated circuits for different design specifications [ABET Criterion 3c]
Outcome 4: Ability to use CAD tools in the design and verification of digital integrated circuits [ABET Criterion 3k]
Outcome 5: Ability to function as an effective team member [ABET Criterion 3d]
Outcome 6: Ability to document and communicate design efforts effectively using written reports [ABET Criterion 3g]
Prepared by: Dr. Muhammad E. Elrabaa, November 12, 2006.
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