Sadiq M.
Sait, K. Elleithy and M. Hassan.
`Formal Synthesis of VLSI Layouts from Algorithmic Specifications'.
International Journal of Computer Systems: Science and Engineering
UK, Vol. 11, Number 2, March 1996, pp 67-81.
K. Elleithy,
Sadiq M. Sait and M. Hassan.
`Formal Design of VLSI Systems'.
Fifth International Conference on Microelectronics,
ICM'93, December 1993, pp 214-219.
Sadiq M.
Sait, K. Elleithy, and M. Hassan.
`Design of a Cell Library for Formal High-level Synthesis',
IEEE Melecon'94, April 1994, pp
1238-1241.
A. A. Amin
and K. M. Elleithy, and M. Hassan, 'A Standard Cell Library for Asynchronous
Event Logic',
The Seventh International Conference on Microelectronics,
Kuala Lumpur, Dec. 19-21, 1995.