COE 202 - Term 131

(Last edited: Friday, December 27, 2013 02:23:17 PM)

Office Hours:   U/T/R   09:00 AM - 10:00 AM or by appointment

• Announcements:

1. Check your attendance so far and your scores so far.
2. Quiz # 01 will be on Thursday 19/09/2013.
3. Quiz # 02 will be on Thursday 26/09/2013.
4. Problem solving sessions will be on Monday 30/09/2013 and Wednesday 02/10/2013 between 12:10 PM and 01:00 PM at room 24-120.
5. Major Exam I will be on Saturday 05/10/2013 at 01:30 PM at room 59-1001.
6. Check out sample major exam I for practice. Also, check out minterms/Maxterms practice problems.
7. Problem solving sessions will be on Monday 28/10/2013 and Wednesday 30/10/2013 between 12:10 PM and 01:00 PM at room 24-174. (Practice Problems)
8. Quiz # 03 will be on Tuesday 05/11/2013.
9. CAD # 01 is due on Tuesday 19/11/2013.
10. Dr. Yahya Osais will conduct the lecture on Sunday 17/11/2013. (Copy of Dr. Osais' MSI explanation)
11. Quiz # 04 will be on Tuesday 26/11/2013.
12. Problem solving sessions will be on Monday 25/11/2013 between 12:30 PM and 2:00 PM at room 22-130, and Thursday 28/11/2013 between 12:15 PM and 2:00 PM at room 22-130. (Practice Problems) (Copy of Dr. Osais' 1st session)
13. Check out sample major exam II for practice.
14. Check out the Timing Diagram Example (picture provided by Mahdi Al-Ibrahim).
15. Quiz # 05 will be on Tuesday 17/12/2013.
16. CAD # 02 is due on Sunday 22/12/2013.
17. Problem solving sessions will be on Wednesday 18/12/2013 and Monday 23/12/2013 and Tuesday 24/12/2013 at 12:15 PM at room 24-114. Note that the sessions will not be a repeat (i.e., they are 2 different sessions).
18. Check out the sequential circuit design problems and solutions.
19. Check out sample final exam for practice. Also, check out the T122 final exam for practice.

• Class Notes:

      Topic 1: Introduction                     Topic 3: Combinational Logic-1            Topic 4: Combinational Circuits-1            Topic 4: Combinational Circuits-4            Topic 5: Sequential Circuits-4

      Topic 2: Number system-1            Topic 3: Combinational Logic-2            Topic 4: Signed Numbers                        Topic 5: Sequential Circuits-1                   Topic 6: Memory/PLD

      Topic 2: Number system-2            Topic 3: Combinational Logic-3            Topic 4: Combinational Circuits-2            Topic 5: Sequential Circuits-2

      Topic 2: Number system-3            Topic 3: Combinational Logic-4            Topic 4: Combinational Circuits-3            Topic 5: Sequential Circuits-3

      Propagation Delay Calculation        Equivalent States

   

• Homeworks: (Late submission NOT accepted)

    HW # 01    HW # 01 Solution                                    CAD Assignment # 01

    HW # 02    HW # 02 Solution                                    CAD Assignment # 02

    HW # 03    HW # 03 Solution

    HW # 04    HW # 04 Solution

    HW # 05    HW # 05 Solution

 

• Quiz Solution:

    Quiz # 01 Solution

    Quiz # 02 Solution

    Quiz # 03 Solution

    Quiz # 04 Solution

    Quiz # 05 Solution

 

• Miscellaneous:

    Course Syllabus

    Support Material (PDF files)

    K-Map Minimizer Tool

    LogicWorks Tool    LogicWorks Tutorial   LogicWorks Example (7-Segment Display)

    Attendance so far            Scores so far

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