List of projects (this is a growing list so keep checking)

 

Advisor        Assoc. Prof. Adznan B. J.

 

1.    Speech Analysis For Vocal Tract Handicapped Patient

 

ProjCode: Adznan1

 

Aim of this senior project is to design a simple system to be able to analyze the speech signals utter by vocal tract handicapped.

 

Way to go about

       Get familiar with sound bluster card of 16 or 32 bits

       Select proper microphone and speakers

       Capture the abnormal speech signals

       Obtain the begin and end points

       Use spectral representation of speech signals algorithm

       Made comparison and analyze

 

Pre-requisite

       Very good in C++ programming

       Able to design speech system is an advantage

 

Number of students : two(2)

Duration :            2 Semester or 1 year

 


Advisor        Assoc. Prof. Adznan B. J.

 

 

2.              Voice automated System

 

Aim of this senior project is to design a simple straight forwards linear recognition algorithm of speech recognition system for limited strategic Arabic vocabularies.

 

ProjCode: Adznan2

 

Way to go about

       Get familiar with sound bluster card of 16 or 32 bits

       Select proper microphone and speakers

       Capture the speech signals

       Obtain the begin and end points

       Obtain Spectral coefficients using LPC(linear Predictive coding) techniques

Compress the data

Used Neural or Hidden Markov Models for recognition

 

Pre-requisite

       Very good in C++ programming

       Interest in electronic interfacing design card.

 

Number of students : two(2)

Duration :            2 Semester or 1 year


Advisor        Assoc. Prof. Adznan B. J.

 

 

3.              Speech Synthesizer  - Speaking Computer

 

Aim of this senior project is to design a speaking computer.

 

ProjCode: Adznan1

 

Way to go about

       Get familiar with sound bluster card of 16 or 32 bits

       Select proper microphone and speakers

       Capture the speech signals

       Obtain the begin and end points

       Design an algorithm of synthesizer processor

 

Pre-requisite

       Very good in C++ programming

       Interest in electronic design interfacing card

 

Number of students : one(2)

Duration :            2 Semester or 1 year


Advisor name:  Wasim Raad

 

Project code: Raad1

 

Project title:  A  Java  smart  card  based system for e-business &  loyalty  applications

 

Project Description: The project is based around the JAVA Cyberflex toolkit  provided by Schlumberger  which includes a Java smart card reader+software development system to develop applications  in JAVA  to be programmed on JAVA  real smart  cards  for secure e-business applications as well as loyalty which means adding points on the card for every transaction.

Project prerequisite: Knowledge of JAVA  & senior standing.

Number of students: 1

Number of semesters:1 

 


Advisor name:  Wasim Raad

 

Project code: Raad2

 

Title:  Design & implementation of an ISO microcontroller based smart  card reader/Writer

 

Description: The project aims at designing & implementing an ISO compatible  Smart  card reader/Writer  based on 8051 microcontroller  which can  program &  read ISO 7816  smart  cards  using the PC.

prerequisite: COE 400

number of semesters: 2

Number of students:2


Supervisor: Dr. Muhammad Elrabaa

 

Project Title: Design of a standard-cell library

 

Project code: StdCLib

 

Description: To design a comprehensive standard-cell library. The expected outcome is a complete cell representation (schematic, layout, spice netlists, HDL description, timing information for several technologies).

 

prerequisite: COE 360, knowledge of Magic is highly recommended though not a must.

 

number of semesters: 1 for a  2-students team and 2 for 1 student

 

Number of students:1 or 2 (see above note regarding duration)


Supervisor: Dr. Muhammad Elrabaa

 

Project Title: Design and Simulation/Emulation of an ad-hoc Mobile (wireless) Network

 

Project code: MobNet

 

Description: To design a simple small-to-mid size ad-hoc network of mobile stations. This includes implementing a proper routing algorithm and simulating/emulating the design. Also the user interface to setup such a network is to be built.

 

prerequisite: COE 441, COE 442 and  knowledge of an appropriate language (Java, visual C++ or even visual Basic).

 

Number of semesters: 1

 

Number of students: 3


Advisor Name: Alaeldin Amin

 

Project Code: Amin 

 

Project Title: Design of a Java Applet to Model Division Algorithms

 

Objectives & Description :

 

This can be used as an educational tool for computer arithmetic/computer architecture courses. The java applet will be given two numbers (a dividend and a divisor) and the applet should show the stepwise behavior of a user-selectable division algorithm. Several algorithms will be studied and implemented, e.g. restoring, non-restoring, SRT, High-Radix, Newton-Raphson, etc.

 

The students are expected to first conduct a literature survey of division algorithms.

 

 

Prerequisite: COE 308 and Good Knowledge of Java

 

Number of students: 2

 

Number of semesters: 1 term project

 


Supervisor: Dr. Farukh Khan

 

Project Title: Behavior of Routing Algorithms

Project Code: Farukh


 
This project involves: simulating a network and studying the application of different types routing algorithms.  The project will require developing a
visual interface for displaying the evolution of routes over time.  The project will also analyze the relative performance of different routing strategies.

 

 

Duration: 1 or 2 semsters


Students: 2

 

Prereqs.: COE442, ICS353, facility with C and Unix


Supervisor: Prof. M. Ibrahim

 

Title :  The Implementation of RSA

Encryption over a Network

 

Code : Ibrahim-RSA

 

Project Description :

Digital signature is the match of handwritten signature in the electronic message systems. In this project, the student will be introduced to one of the most popular cryptography techniques used in Internet and will work on the software and hardware implementation of this technique. In addition, he will experience the transfer of encrypted data over a network. The project will be a distinguishable opportunity for students to work with Network Security Area.

 

Semester(s): 2

Student(s)  : 1 with GPA > 2.5

Skills : Basic Java Programming , COE 442


Supervisor: Prof. M. Ibrahim

 

Title : Cracking Affine Encryption

 

Code : Ibrahim-Affine

 

Description:

Data encryption is critical for internet applications that require high security, such as e-commerce. The robustness of any encryption techniques depends on how difficult it is to break such techniques. In this project, the student will learn how to crack one of the oldest known cryptography techniques. The main objective of this project is to study and simulate the process of breaking this technique.

 

Semester(s): 2

Student(s)  : 1 with GPA > 2.5

Skills : Basic Visual-Basic Programming , Java or C++.

 

 

 

 


Supervisor: Prof. M. Ibrahim

 

Title : The Simulation of an Elliptic Curve

  Cryptosystem

 

Code : Ibrahim-ECC

 

Description : 

Cryptography and Protocol Engineering are growing areas in Network Security. In this project, the student will be introduced to one of the most recent public key cryptography techniques. In addition, he will deal with Diffe-Hellman Exchange Key Protocol and software and hardware implementation issues. The project represents a real opportunity to work with the world of network security. 

 

Semester(s): 2

Student(s)  : 1 with GPA>2.5

Skills : Visual Basic or Java


Supervisor: Dr. Waheed

Title: Design and performance analysis of a network caching infrastructure

Project code: Waheed_4
Number of students: 1

# of semesters: 1

 

Project Description:


Proxy caches are an essential part of Internet infrastructure that serve many purposes, including bandwidth saving and latency hiding. This project requires the student to design a caching infrastructure using two caches: Microsoft Proxy Cache and Squid proxy cache. This infrastructure will be demonstrated using a simulation tool as well as in a lab using appropriate tools, such as DummyNet and IP aliasing. Some performance experiments will have to be designed to analyze the efficacy of this infrastructure.


Supervisor: Dr. Waheed

Project Title: Waheed_5: Design and performance analysis of a streaming media architecture
Project Code: Waheed_5

Number of students: 1

Number of semesters: 1


Project Description:

Streaming media servers are used to distribute compressed videos either on-demand or on-line to multiple receivers over the Internet. Server needs to meet several performance and quality-of-service constraints for such applications. In this project, we will design an Infrastructure (server, clients, and a simulated WAN) using at least two widely used streaming servers: Quicktime server and WindowsMedia server. Infrastructure will have to be demonstrated both in simulation as well as it will be implemented in a lab environment with appropriate performance measurements.


Supervisor: Dr. Waheed

Project Title: Design and performance evaluation of a cluster of computers
Project Title: Waheed_6

Number of students: 1

Number of semesters: 1


Project Description:

Cluster of computers based parallel architectures have become popular as they provide an alternate for high-end, high-priced, tightly-coupled concurrent and vector supercomputers. This project requires the student to develop a loosely-coupled cluster using available desktop PCs and a local network. There will be three flavors of this cluster: cluster of linux platforms; cluster of FreeBSD platforms, and a cluster of Windows platforms. Appropriate software tools will have to be installed to demonstrate the three types of clusters. A number of example programs will be used to evaluate the correct functionality and performance of these clusters.


Supervisor: Dr. A. El-Maleh

Project Title: Design, Modeling and Simulation of a small  8-bit processor using Logic Works Simulator
Project Code: El-Maleh-1

The project involves the design and modeling of a small processor using Logic Works. The processor is sufficiently simple and will be used for educational purposes for the computer organization and assembly language programming course. A small instruction set consisting of eight instructions will be selected by the students for the processor to simplify its design. Then, the processor data path will be designed using a single-bus architecture. The control unit will be designed using both the hardwired and  microprogrammed approach. The whole CPU has to be modeled and tested with interface to memory.

The project involves the following tasks:

1. Instruction set selection
2. Design of instruction format.
3. Data path design.
4. Control unit design
          a. Hardwired approach
          b. Microprogrammed approach
5. Design modeling using Logic Works.
6. Design verification by Logic Works simulation.

Student(s): Two
Number of semesters: Two
Pre-requisite: Excellent performance in COE 200 and COE 205.

Project Title: An Efficient Test Compression Technique for Multiple-Scan Chain Designs

Project Code: El-Maleh-2

With today’s technology, it is possible to build complete systems containing millions of transistors on a single chip.  Systems-on-a-chip (SOC) are comprised of a collection of pre-designed and pre-verified cores and user defined logic (UDL). As the complexity of systems-on-a-chip continues to increase, the difficulty and cost of testing such chips is increasing rapidly. One of the challenges in testing SOC is dealing with the large size of test data that must be stored in the tester and transferred between the tester and the chip.  The amount of time required to test a chip depends on the size of test data that has to be transferred from the tester to the chip and the channel capacity. The cost of automatic test equipment (ATE) increases significantly with the increase in their speed, channel capacity, and memory.  As testers have limited speed, channel bandwidth, and memory, the need for test data reduction becomes imperative. One way to achieve test data reduction is by compression. In test data compression, the objective is to reduce the number of bits needed to represent the test data. For test data compression, it is essential that the compression is lossless. The compressed test data will be stored in the tester and decompressed in the circuit under test. In this project, the students will investigate a new technique for test data compression and demonstrate its feasibility. They will implement the new technique and run experiments on benchmark circuits to evaluate it.

 

Name of Supervisor: Aiman El-Maleh
Status: Taken
Action Plan: To be submitted
Progress Report: To be submitted
Attendance Report: Satisfactory
Student(s): Two
Number of semesters: Two
Pre-requisite: Excellent C programming skills. 

 

Name of Supervisor: Aiman El-Maleh

Project Title: Modeling Parametrizable Arithmetic Blocks in VHDL and Mapping them into FPGAs

Project Code: El-Maleh-3

The projects involved modeling parametrizable arithmetic blocks including different types of adders and multipliers and mapping them into FPGAs. The student will first model the required arithmetic block and verify that it works using simulation. Then, he will prototype the design using available FPGA boards, verify the functionality and measure the circuit performance.   


 Student(s): One

Number of semesters: Two

Pre-requisite: Prior VHDL knowledge.


 


Project Title: Modeling and Simulation of a small  8-bit microprogrammed processor using VHDL

Project Code: El-Maleh-4

The project involves modeling of a small microprogrammed processor using VHDL. The processor consists of 19 instructions. It has been design using the hardwired approach and modeled using VHDL. It has also been designed using the microprogrammed approach and modeled using Logic Works.  In this project, the student will understand the existing design, verify its correctness, and then model the microprogrammed control  unit in VHDL and interface it with the already existing data path modeled in VHDL. He will also test the whole CPU design and verify its correctness.

Name of Supervisor: Aiman El-Maleh

Student(s): One

Number of semesters: Two

Pre-requisite: Prior VHDL knowledge. 


Supervisor: Dr. Farukh Khan

 

Project Title: The journey of raw audio to

compressed audio (and back).

 

Project code: Farukh2

 

Description:

 

In this project, the student will explore all stages of audio processing, from the stage of sampling to final audio files conforming to well-known standards. The student will develop code for different functions, including compression and play of different bit-rate audio files.  The student will also study the appropriateness of competing standards in terms of resource usage, fidelity,
implementation in hardware etc.

 

Duration: 1 or 2 semesters

Students: 1

Prereqs.: Facility with C (or another language).


Name of Supervisor(s)  Mostafa H. Abd-El-Barr and Salman A. Khan 

 

Project Title: Development of a visual tool for

Fault Tolerant Routing in Hypercubes

 

Project Code: Mos-Sal-012

 

Description: The objective of this project is to develop a visual tool for rotuing in hypercubes in presence of faults. There are different algorithms that are capable of routing information in faulty hypercubes.
These faults are of two types: link failure and/or node failure.


 The student is required to do the following:

 1) Study some existing techniques and related literature.
 2) Develop a software to simulate some of these techniques.
 3) Develop a visual tool.

 4) Study the possibility of improving the performance of some existing fault-tolerant routing schemes


 No. of students: 1

 No. of semesters: 1

 Pre-req: Senior Standing. Stength in Visual Basic or any vsiual language.


Title: Streaming Media for Web Based Training

ProjCode: Smedia1

 

Streaming media technology enables real time or on demand distribution of audio, video and multimedia on the Internet. The primary advantage of this technology is that large audio and video files can be played as they arrive on the computer rather than having to wait for the file transfer to complete. This makes the user interface much more responsive.

 

The objective of this project is to look into the background in streaming media technology, discuss its standards, the current state of the technology, and experiment with Real Networks and Microsoft products for development of sample Web Based Training content.

 

Name of the advisor:    Ali S. Hussain

Name of the co-advisor:        Dr. Sadiq M. Sait.

Number of students:    1 or 2

Office Location:            22-334

Tel:                                3550

E-mail:                           hussain@ccse.kfupm.edu.sa

 


Title: Investigation of Distance Learning Requirements

 

ProjCode: Smedia2

 

In a society where the emphasis of education and learning is high, both amongst women and men, and with limited facilities to women folk in particular (for example, lack of technical schools) it will be possible to broaden the scope of learning in both sexes by providing facilities for remote access to class rooms, lectures, and other material through the Internet. The objective of this project is to investigate the need for the establishment of such classrooms (practicality, feasibility), etc, and propose design requirements for its layout, bandwidth and technical requirements and experiments with distance learning tools.

 

 

Name of the advisor:    Ali S. Hussain

Name of the co-advisor:        Dr. Sadiq M. Sait.

Number of students:    1 or 2

Office Location:            22-334

Tel:                                3550

E-mail:                           hussain@ccse.kfupm.edu.sa

 


Advisors: Aleeldin Amin and R. E. Abdel-Aal

 Project Code: Amin-Radwan

 

Project Title: Design and Modeling of ASIC Abductive Networks

 

Project Description:

Similar to neural networks, abductive networks provide a self-organizing, data-based, machine learning tool for modeling underlying input-output relationships through supervised learning. However, training and configuration of abductive network models are faster and more straight forward, and they also have better explanation capabilities.  Abductive network modeling has been used in a wide range of applications, including weather forecasting, medical diagnostics, and online vibration monitoring.

While processing elements in neural networks are restricted by the analogy to the simple human neuron, abductive networks employ various types of more powerful polynomial functional elements organized in layers in a feed-forward fashion. The element types are individually chosen during training for optimum prediction performance. The network can be implemented in software, but demanding real-time applications require hardware implementations.

This project aims at developing architectural concepts as well as designing and modeling of  circuit building blocks for implementing a generic ASIC abductive network. The design should contain a number of functional elements of each of the various types; i.e. Normalizer, Unitizer, White, Single, Double, and Triple elements, together with means to load-in their coefficients derived during training and to interconnect them to implement a desired abductive model. To ensure adequate numerical accuracy, floating point arithmetic will be used throughout.

 

Project Pre-requisite: COE 308 and good knowledge of VHDL and Major GPA>3

 Number of students: 2

 Number of semesters: 1 term project


Supervisors :  Dr. A. R. Naseer   &  Dr. Sadiq M. Sait

 

Title  :   VHDL Modelling and FPGA implementation of 10/100 Mbps Ethernet MAC

ProjCode: EMAC

 

Brief Description : 

This  project involves the modeling  of a 10/100 Mbps Ethernet MAC using VHDL and  implementation of the resulting design  using Xilinx  FPGAs.  Ethernet MAC is a part of Ethernet device which controls the transmission and reception of data packets  based  on CSMA/CD protocol. 10/100 Mbps Ethernet MAC consists of two parts, the Transmitter and the Receiver. In OSI communication model,Ethernet MAC is included in the data link layer. The 10/100 Mbps Ethernet MAC performs the following main functions:

-        Providing a connection path between physical layer and network layer for data transfer process.

-        Packeting data using 802.3 standard data packet format.

-        Preamble generation and removal

-        Collision detection using CSMA/CD protocol

-        Detecting error in received data packet

-        Automatic 32-bit CRC generation and checking

-        Controlling data flow in Ethernet NIC

 

Pre-requisite :   COE 442, Knowledge of VHDL coding & FPGA mapping is desirable

Duration  :  One semester

# of students  required  :   Two in the project group


Supervisors :  Dr. A. R. Naseer   &  Dr. Sadiq M. Sait

 

Title  :  VHDL  design and FPGA implementation of a RISC processor

 

Brief Description :

 

This project involves the design of a 16/32-bit RISC processor using VHDL and implementing the resulting design using Xilinx FPGAs.  The major tasks to be performed in the RISC processor   project  are :

 

-        Constructing an instruction set architecture,

-        Determining the structure of internal registers and memory, 

-        Designing the pipelined Arithmetic Unit

-        Designing the pipelined instruction processing unit  with branch detection and data hazard detection logic

 

Pre-requisite :   COE 308

 

Desirable  :   Knowledge of VHDL coding & FPGA mapping

 

Duration  :  One semester

 

 

# of students  required  :   4 ( 2 students per group) in the project


Supervisors :  Dr. A. R. Naseer   &  Dr. Sadiq M. Sait

 

Title  :    Design  and Implementation of High Speed Multipliers using

     LUT based FPGAs.

 

Brief Description : 

 

This  project involves the  study of various high speed multiplication algorithms and  implementation of  these using LUT based FPGAs with emphasis on  configurable blocks to construct multipliers.  These multipliers find extensive use in Image/Video processing applications.

 

Pre-requisite :   Senior standing

 

Desirable  :   Knowledge of VHDL coding & FPGA mapping

 

Duration  :  One semester

 

# of students  required  :   Two in the project group


Supervisors :  Dr. A. R. Naseer   &  Dr. Sadiq M. Sait

Title  :    Survey and Evaluation of  Function Decomposition techniques targeted for FPGAs

 

Brief Description : 

 

Function decomposition is an important step in the mapping of a function onto FPGA CLBs. A function is said to be realizable if it can be directly realized by a CLB, otherwise it is termed  to be unrealizable. Decomposition step in the mapping process is used to convert an unrealizable function into a set of realizable sub-functions, i.e., sub-functions which can be realized by individual CLBs.  As decomposition is  computationally intensive, several methods have been proposed to speedup this process. This project involves the survey and evaluation of the function decomposition techniques targeted for FPGAs. This work can be extended  to develop a new faster  heuristic based decomposition technique**.

 

Pre-requisite :   Senior standing  with major  GPA B+ or higer

Desirable  :   Knowledge of  ‘C’ programming &  FPGA architecture

 

Duration  :  One/two  semester**(s)

 

# of students  required  :   Two in the project group


Supervisors :  Dr. A. R. Naseer   &  Dr. Sadiq M. Sait

Title  :    Survey and Evaluation of  FPGA mapping techniques 

 

Brief Description : 

 The Field Programmable  Gate Array is a relatively new technology that allows  circuit designers to produce ASIC chips without going through the conventional fabrication process. Short turnaround time and low manufacturing  cost have made FPGA technology popular for rapid  system prototyping and low-to-medium volume applications. The increase in complexity of FPGAs in recent years have made it possible to implement data path oriented designs onto FPGAs. Further, recent LUT based FPGA architectures offer high performance potential and make FPGAs a viable technology for performance critical applications.  The project involves  survey and evaluation of  the techniques for mapping  Data  path and Control part of the design onto FPGAs.  This work can be extended to develop  a  faster technology mapper for LUT based FPGAs**

 

Pre-requisite :   Senior standing  with major  GPA  B+ or higher

Desirable  :   Knowledge of  ‘C’ programming &  FPGA architecture

Duration  :  One / Two semester**(s)

# of students  required  :   Two in the project group