Proceedings of
the 13th ACM Great Lakes Symposium on VLSI
, pages 237-240,
Power-time flexible architecture for GF(2k) elliptic curve cryptosystem computation
Adnan Gutub and Mohammad K. Ibrahim
ABSTRACT
New elliptic
curve cryptographic processor architecture is presented that result in
considerable reduction in power consumption as well as giving a range of
trade-off between speed and power consumption. This is achieved by exploiting
the inherent parallelism that exist in elliptic curve point addition and
doubling. Further trade-off is achieved by using digit serial-parallel
multipliers instead of the serial-serial multipliers used in conventional
architectures. In effect, the new architecture exploits parallelism at the
algorithm level as well as at the arithmetic element level. This parallelism
can be exploited either to increase the speed of operation or to reduce power
consumption by reducing the frequency of operation and hence the supply
voltage.
Categories
and Subject Descriptors
B.2.4 High-Speed
Arithmetic (Algorithms, Cost/performance)
C.5.4 VLSI
Systems
General
Terms
Algorithms,
Measurement, Performance, Design, Security.
Keywords
Elliptic Curve Cryptography, Projective
Coordinate arithmetic, Parallel architecture, Crypto-Systems Power-time
tradeoff.