COE360: Principles of VLSI Design

 

Course Outline

Course Handouts:

        Hand outs are in Bldg.21 and include; semiconductor basic concepts, Unix basic commands, and     

            Magic Tutorials. 

        The handout on basic digital circuit's parameters is here.

        Some  course notes on scaling

Project Description and Resources ...

       042 project description

 

       A Short course on SPICE (and WinSpice3)

 

       Full Spice3 user's manual (link). Also check my shared folder for a WINSPICE manual.

 

       Download a self-extracting WinSpice (includes a full user's manual) from \\coe-elrabaa\SharedFolder\winspice.

 

       Spice Technology files: 0.5m, 5V Technology0.35m, 3.3V Technology ,

                                                   0.25m, 2.5V Technology and 0.18m, 1.8V Technology

 

       WinSpice example files: DC analysis of an NMOS inverter & Transient analysis of the same circuit

 

       5Spice Installation folder (just copy to your Z drive)

 

         Magic Resources (These are from Dr. El-Maleh's web and will open in a separate window)

                  Setting up your Magic Account

                   Magic Tutorials: tut1, tut2, tut3, tut4, tut5, tut6, tut7, tut8, tut9, tut10, tut11

                   Magic & Irsim source code (magic6.5)

                   Download Magic for W2000 from \\coe-elrabaa\SharedFolder\Magic\Magic for W2000

                   Download Magic for XP from \\coe-elrabaa\SharedFolder\Magic\Magic for XP

                   Magic layers  (Cheat-sheet)

                 Also there are two shared folders on my machine's C drive (\\coe-elrabaa):

                     one contains the Magic Technology files for the three technologies (TechFiles)

                      and another for a self-extracting WinSpice (Spice 3 for windows). The technology

                    files include a PAD_ESD standard cell library. The  documentations for the PAD library

                      and for logic standard cells (useful to see how a professional layouts looks like).

                       

 

Here are some practice layouts ...

 

  Here is an example of a Phase II project Report

 

Assignments & Quizzes

        Assign #1    

 

        Assign #2  

       

        Assign #3     

        Assign #4 

   

        Assign #5   out of 20    Due on Sat. 15/5/2005

 

                   

 

          Take home Quiz #3 (Spice simulation of a CMOS inverter)     

          

        Take home Quiz #4    

        

        Take home Quiz #5  

 

        Assign #6     

  Exams

       Major Exam 1: On Sunday, Mar. 27th, 2005, 6:30 - 8:00 PM,  room (24-112)

       Major Exam 2: On Friday 20/5/2005, 7:00 - 8:30 pm , Room 22-119

       Final Exam : On Tuesday 7/6/2005, 7:00 - 9:00 pm , Room 6-125

 

    Help Session On Monday 6/6/2005, 10:00 AM , Room 22-119

 

  Check your marks

        Grades