COE360 Course Project (021)

Dr. Muhammad Elrabaa

Design an 8-bit adder [c1] using AMI’s 0.5 µm technology with the following specifications:

1. All gates should have symmetrical noise margins,

2. Minimum area such that the operating frequency is 500 MHz at a load capacitance of 2 pF per output,

3. Input capacitance of less than 50 fF.

The deliverables for this project are as follows:

1. Phase I: Logic Design Due Monday 6/9/1423 (11/11/2002)

This is the gate level implementation of the Adder. This part carries 5% and there will be a bonus for logic verification (e.g. using Logic Works or HDL).

2. Phase II: Circuit Design Due Monday 12/10/1423 (16/12/2002)

This is the transistor level implementation of the adder. This part carries 5% and includes all the SPICE files simulation results.

3. Phase III: Mask Design (layout) Due Wednesday 12/11/1423 (15/1/2003)

This is the physical mask level (i.e. layout) implementation of the adder. It carries 10% and includes the post-layout verification using IRsim and SPICE simulations. All layouts should be DRC clean and clearly labeled. A short final report documenting the whole project should be submitted and an exit interview shall be conducted.