COE544:   Design of VLSI Integrated Processors


Course Outline

Course Notes: The following chapters are from the ASICS Book


Ch1    Ch2 Ch3    Ch4   Ch5   Ch6   Ch7  Ch8 Ch9 Ch10  
Ch11     Ch12    Ch13 Ch14  Ch15   Ch16 Ch17 Verilog   Notes VHDL  Notes  


The complete book is at


     It is also available on my shared folder on my machine \\coe-elrabaa

Hand outs are in Bldg.21 (in the COE360 file of Dr. Muhammad Elrabaa) and include; Unix basic commands, and Magic  Tutorials. Also the handout on review of basic digital circuit parameters is here.

Project Resources

       A Short course on SPICE (and WinSpice3)

       Full Spice3 user's manual

       Spice Technology files: 0.5m, 5V Technology0.35m, 3.3V Technology ,

                                                   0.25m, 2.5V Technology and 0.18m, 1.8V Technology

Assignments & Quizes

        Assignment 1

        SPICE Assignments:


                    1.  Assignment1


                    2. Design a 4-bit CLA with 0.5 pF load capacitance, minimum area and power with an operating    

                        frequency of 1 GHz. Gates must have symmetrical noise margins. Use the 0.18 m technology.


        Layout Assignments:


                    1. Produce a layout of the C3 gate in your CLA-4 using Ledit. Check your layout against a

                        schematic (LVS)


                    2. Produce a symbolic layout of the CLA-4 adder


        Assignment 4 and 5


        Project Assignment 1


        Project Assignment .. 



           Next Quiz: On .....


       Midterm Exam : .....


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