COE360, Quiz # 5 (Take home)
Dr. Muhammad Elrabaa
1) Design an AOI21 CMOS gate (I.e. obtain its schematic and the devicesí sizes) such that it will have equal noise margins and an average delay of 100 pS. Assume a fan out of 3 and a total wiring capacitance of 200 fF. Use the 0.5 U technology (i.e. Lambda = 0.3 U) and Spice3 to design this circuit.
2) Draw the layout of this gate using Magic and simulate it using IRSim or Rsim.
3) Extract the Spice netlist from the Magic layout and re-simulate using the extracted netlist.