ICS 233  :  Computer Architecture & Assembly Language Prog   (3-0-3)


Course Details

Term       :       Spring    Term 2007-08 (T072)     

Section   :        2 

Day & Time :  UT 11.00 AM to 12.15 PM  

Location       :  24/178

Catalog Description :

Machine organization; assembly language: addressing, stacks, argument passing, arithmetic operations, decisions, modularization; Input/Output Operations and Interrupts; Memory Hierarchy and Cache memory; Pipeline Design Techniques; Super-scalar architecture; Parallel Architectures.


Pre-requisite :     COE 202, ICS 201

Text Book :          

·       David A. Patterson and John L. Hennessy, Computer Organization & Design, The Hardware/Software Interface, Third Edition, Morgan Kaufmann Publishers, 2005. ISBN: 1-55860-604-1.

·    Robert L. Britton, MIPS Assembly Language Programming, Pearson Prentice Hall, 2004.


1.  Sivarama P. Dandamudi, “Guide to RISC Processors for Programmers and Engineers”, Springer Science, 2005, ISBN 0-387-21017-2 

2.  MIPS32 Architecture for Programmers, Volume I: Introduction to the MIPS32 Architecture, MIPS Technologies Inc, Revision 2.50, July 2005.

3.   MIPS32 Architecture for Programmers, Volume II: The MIPS32 Instruction Set, MIPS Technologies Inc, Revision 2.50, July 2005.

4.  MIPS32 Architecture for Programmers, Volume III: The MIPS32 Privileged Resource Architecture, MIPS Technologies Inc, Revision 2.50, July 2005.


Course Objectives :


Towards the end of this course, students should be able to:

·        Describe the instruction set architecture of a MIPS processor

·        Analyze, write, and test MIPS assembly language programs

·        Describe the organization/operation of integer and floating-point arithmetic units

·        Design the datapath and control of a single-cycle processor

·        Design the datapath and control of a pipelined processor and handle hazards

·        Describe the organization/operation of memory and caches

·        Analyze the performance of processors and caches


Detailed Syllabus

Course Topics & Lecture Break down


Course Topics

Topic Reference in the Text Book


Introduction to computer architecture, assembly and machine languages, components of a computer system, memory hierarchy, instruction execution cycle, chip manufacturing process, technology trends, programmer’s view of a computer system.

Chapter 1

2 , 3

Instruction set design, RISC design principles, MIPS registers, instruction formats, arithmetic instructions, immediate operands, bit manipulation, load and store instructions, byte ordering, addressing modes, flow control instructions, pseudo-instructions, procedures and runtime stack, call and return, MIPS register conventions, alternative IA-32 architecture.

Sections 2.1 – 2.9

Sections 2.13, 2.15 – 2.18

Sections 3.2 – 3.3

Appendix A.9 – A.10


CPU performance and metrics, CPI, performance equation, MIPS as a metric, Amdahl’s law, benchmarks and performance of recent Intel processors.

Chapter 4


5 , 6

Integer multiplication, integer division, floating point representation, IEEE 754 standard, normalized and de-normalized numbers, zero, infinity, NaN, FP comparison, FP addition, FP multiplication, rounding and accurate arithmetic, FP instructions in MIPS.

Sections 3.4 – 3.6

Sections 3.8 – 3.9

7 , 8,9

Designing a processor, register transfer logic, datapath components, clocking methodology, single-cycle datapath, main control signals, ALU control, single-cycle delay, multi-cycle instruction execution, multi-cycle implementation, CPI in a multi-cycle CPU.

Sections 5.1 – 5.5


Pipelining versus serial execution, MIPS 5-stage pipeline, pipelined datapath, pipelined control, pipeline performance.

Sections 6.1 – 6.3


Pipeline hazards, structural hazards, data hazards, stalling pipeline, forwarding, load delay, compiler scheduling, hazard detection, stall and forwarding unit, control hazards, branch delay, dynamic branch prediction, branch target and prediction buffer.  

Sections 6.4 – 6.6

14 , 15

Cache memory design, locality of reference, memory hierarchy, DRAM and SRAM, direct-mapped, fully-associative, and set-associative caches, handling cache miss, write policy, write buffer, replacement policy, cache performance, CPI with memory stall cycles, AMAT, two-level caches and their performance, main memory organization and performance. Virtual memory, address mapping, page table, handling a page fault, TLB, virtual versus physical caches, overlapped TLB and cache access.

Sections 7.1 – 7.6


Also Refer CD  –  “In More Depth Section” of all Chapters


Software Tools used in Lab/Projects

·        PCSpim simulator: runs MIPS-32 assembly language programs

PCSPIM – A MIPS32 Simulator  can be downloaded from  http://www.cs.wisc.edu/~larus/spim.html,

Also refer Appendix A in Patterson and Hennessy Text Book.

·        MARS Simulator: runs MIPS-32 assembly language programs (visit MARS homepage)

·        Logisim Simulator: educational tool for designing and simulating CPUs (visit Logisim homepage)



Attendance Policy 

Because absence from class will prevent a student from getting the full benefit of a course, and because in many courses each student's involvement contributes to the learning process for all other students in the class, attendance is mandatory for every exercise of a course in which a student is registered. Excessive absences may result in  withdrawal from the class.  

A regular student should attend all classes and laboratory sessions. A student may be discontinued from a course and denied entrance to the final examination  if his attendance is less than the limit determined by the University Council. 

A regular student will  not be allowed to continue in a course and to take  the final examination  and will be given a DN grade if his unexcused absences are more than 20% of the lecture and laboratory sessions scheduled for the course (Refer Undergraduate Bulletinsection on Attendance and withdrawal from study pp. 25-27  for more details). 


Academic Dishonesty Policy 

In order for instructors to fairly assess the quality and quantity of a student's learning (through course grades) as determined by work that students represent as their own, a relationship of trust between instructor and student is essential. Because violations of academic integrity most often involve, but are not limited to, efforts to deceive instructors, they represent a breach of the trust relationship between instructor and student, and undermine the core values of the university. For these reasons, the University and its instructors treat issues of academic dishonesty as serious violations of academic trust, and conduct rigorous investigations of students suspected of committing such acts. 


  • the illegitimate use of materials in any form during a quiz or examination
  • copying answers from the quiz or examination paper of another student
  • plagiarizing (submitting as one's own ideas the work of another) or falsifying materials or information used in the completion of any assignment which is graded or evaluated as the student's individual effort
  • submitting the same work for more than one course without the consent of the instructors of each course in which the work is submitted
  • copying material from a web page and submitting it as one's own work
  • quoting extensively from a document without making proper references to the source

If  a student is found  committing  such acts in a quiz or  home assignment or exam or  term paper, he will be given a grade 0 in that part of the course.


Tentative Grading Policy and Exam Dates:                                         

  1. Quizzes                               6%
  2. Homework Assignments       4%
  3. Lab Assignments                 20%
  4. Projects                              20%
  5. Major Exam I                      15%  (Sunday,  6th April,  2008 -  6.30pm to 8.30pm )
  6. Major Exam II                     15%  (Tuesday, 20th  May, 2008 -  6.30pm to 8.30pm)
  7. Final Exam                          20%   (as per the University Exam Schedule)


Office Hours :     Saturday, Sunday, Tuesday   12.15 PM to  1.00 PM