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COE 501  :  Computer Architecture   (3-0-3)

Course Details

Term       :       Spring    Term 2007-08 (T072)     

Section   :      

Day & Time :  UT 5.00-6.15 P.M.  

Location       :  22/134

Catalog Description :

Classification of Computer Systems, architectural developments, computer performance, Linear and non-linear pipeline design, instruction and arithmetic pipeline, Superscalar processors,   Memory hierarchy, cache and virtual memory, cache coherence, memory system performance, Parallel architectures, performance measures, SIMD and MIMD architectures, interconnection networks

The students are expected to carry out research projects in related field of studies.

 

Pre-requisite :     COE 308  or  Equivalent

 Books:                     

Computer Architecture-A Quantitative Approach,

by J. L. Hennessy and D. A. Patterson, Morgan Kaufmann, Fourth Edition, 2006.


Course Objectives and Outcomes

        To understand performance measures used in computer design

-         understand technology and cost trends in computer design

-         understand how computer performance is measured and reported

-         understand the quantitative principles that computer designers use

        To understand the principles of instruction set design

-         study the statistics of instruction usage by programs executing on a recent instruction set architecture

-         study the statistics of the use of memory addressing modes in programs executing on a recent instruction set architecture

-         study the statistics of the types and sizes of operands used by programs executing on a recent instruction set architecture

-         study in detail the encoding of instructions in a recent instruction set architecture

        To understand basic and advanced pipelining techniques

-         understand basic methods for handling data, control, and resource hazards in single-pipeline processors

-         analyze instruction-level parallelism (e.g., loop unrolling and detailed aspects of instruction dependence)

-         analyze operation and performance of pipelines incorporating dynamic scheduling

-         analyze operation and performance of pipelines incorporating dynamic branch prediction

-         analyze operation and performance of pipelines incorporating multiple-instruction issue

        To understand advanced aspects of virtual memory and cache design.

-         analyze cache timing and use that information in analyzing overall computer performance

-         analyze implementation details of advanced cache features (e.g., write buffers, prefetch buffers, out-of-order fetches)

-         analyze cache and TLB interaction and timing and use that information in analyzing overall computer system performance

          To understand Multiprocessor architectures and Thread Level Parallelism

       -     Understand the models for communication and memory architectures in multiprocessor systems

-     Understand the basic methods for handling  cache coherency problem  in Symmetric shared-memory architectures  (snooping protocols)

-     Analyze the performance of Symmetric shared-memory multiprocessors

-    Understand the basic methods for handling  cache coherency problem in Distributed shared-memory architectures  (Directory based protocols)

-     Analyze the performance of  Distributed  shared-memory multiprocessors

-     Analyze the synchronization mechanisms for multiprocessor systems

-     Understand the basic principles of  Multithreading -  Thread Level Parallelism

-     Analyze the operation and performance of interconnection networks

 

Detailed Syllabus

 

Fundamentals of Computer Design:
The Task of the Computer Designer, Technology and Computer Usage Trends, Cost, Price and their Trends, Measuring & Reporting Performance, Quantitative Principles of Computer Design                                                                                                                             1.5  weeks

Instruction Set Principles:


Classifying Instruction Set Architectures, Memory Addressing, Operations in the Instruction Set, Type and Size of Operands, Encoding an Instruction Set, Role of Compilers            
   1.5  weeks

 

Pipelining:


The Basic Pipeline, Pipeline Hazards, Data Hazards, Control Hazards, Multi-cycle Operations, exceptions                                                                                                               1  week

 

Advanced Pipelining and Instruction Level Parallelism:


Instruction Level Parallelism Concepts, Overcoming Data Hazards with Dynamic Scheduling, Branch Prediction, Hardware Support for Exploiting ILP, Studies of the limitations of  ILP                                                                                                                                 2  weeks

 

Exploiting Instruction-Level Parallelism with Software Approaches:

Basic Compiler techniques for Exploiting ILP, Static branch prediction, Static multiple issue-VLIW approach, Advanced compiler support for exposing and exploiting ILP, Hardware vs. Software Speculation Mechanisms                                                                             3 weeks

 

Memory-Hierarchy Design:


Caches, Cache Performance, Reducing Cache Misses, Reducing Cache Miss Penalty, Reducing Hit Time, Main Memory, Virtual Memory, Issues in the Design of Memory Hierarchies                                                                                                                                              
3 weeks

 

Multiprocessors and Thread-level Parallelism

Characteristics of Application Domains, Symmetric & Distributed Shared-Memory architectures, Performance of   Symmetric and distributed  Shared-Memory multiprocessors, synchronization, Models of  Memory consistency, Multithreading Exploiting  Thread-level Parallelism within a processor, overview of interconnection networks                                                         3 weeks

 

Tentative Grading Policy and Exam Dates:                                         

  1. Home Assignments                   10%
  2. Term Paper                              15%
  3. Term Project                            25%
  4. Midterm Exam                          20%   (9th  April  2008  from 6.30pm to 8.30pm)
  5. Final Exam                               30%    (9th  June   2008  from 7 pm to 10 pm)

 

Office Hours :         Saturday, Sunday & Tuesday   :    12.15 PM to 1.00 PM        

 

Term Paper  Guidelines 

  • Term Paper  involves the following main tasks :

-    Detailed Literature survey on the topic selected (related to Computer Architecture field)

-    Preparation of   the  term  paper

-    Presentation of   the paper  

  • Topics for the term paper can be selected from the following areas (but not limited to these - you can suggest  a current topic of interest) :

- Multi-core Processor Architectures

- Instruction & Data Level Parallelism

- Thread-level Parallelism

- Static & Dynamic Scheduling

- Static & Dynamic Branch Prediction

- Multi-level Caches

- Software Pipelining

- Storage Systems SAN, NAS

- Interconnection Networks & Clusters  

  • Each student is required to select a separate topic from the above list by 15th   March 2008
  • Last date for Submission of the Term Paper  :  11th May  2008
  • Maximum  duration of  the  presentation will be  30 minutes for each student.

 

Mini-project Guidelines
 
  • Term Project  involves the following main tasks : 

    -    Selection of a particular research problem

    -    Project Design & Implementation/simulation     

    -    Preparation of  the Project Report in the form of a IEEE Paper for possible  publication

    -     Presentation of  the Project work 

     

    • Topics for the term project can be selected from the following areas (but not limited to these - you can suggest  a current topic of interest) :

    - Multi-core Processor Architectures

    - Instruction & Data Level Parallelism

    - Thread-level Parallelism

    - Static & Dynamic Scheduling

    - Static & Dynamic Branch Prediction

    - Multi-level Caches

    - Software Pipelining

    - Storage Systems SAN, NAS

    - Interconnection Networks & Clusters

    - Wireless Sensor Networks

     

    • Each student is required to select a current research topic from the above/suggested areas and submit a research project  proposal  by 22nd   March  2008.
    • Last date for Submission of the completed work  :  1st  June  2008
    • Deliverables :  Project Report, source code developed, simulation results, Presentation
    • Presentation will be held in the last week of the term & maximum  duration of  the  presentation will be  40 minutes for each student.

 

Attendance Policy 

Because absence from class will prevent a student from getting the full benefit of a course, and because in many courses each student's involvement contributes to the learning process for all other students in the class, attendance is mandatory for every exercise of a course in which a student is registered. Excessive absences may result in  withdrawal from the class.  

A regular student should attend all classes and laboratory sessions. A student may be discontinued from a course and denied entrance to the final examination  if his attendance is less than the limit determined by the University Council. 

A regular student will  not be allowed to continue in a course and to take  the final examination  and will be given a DN grade if his unexcused absences are more than 20% of the lecture and laboratory sessions scheduled for the course (Refer Undergraduate Bulletin section on Attendance and withdrawal from study pp. 25-27  for more details). 


Academic Dishonesty Policy 

In order for instructors to fairly assess the quality and quantity of a student's learning (through course grades) as determined by work that students represent as their own, a relationship of trust between instructor and student is essential. Because violations of academic integrity most often involve, but are not limited to, efforts to deceive instructors, they represent a breach of the trust relationship between instructor and student, and undermine the core values of the university. For these reasons, the University and its instructors treat issues of academic dishonesty as serious violations of academic trust, and conduct rigorous investigations of students suspected of committing such acts. 

ACTS OF ACADEMIC DISHONESTY INCLUDE, BUT ARE NOT LIMITED TO, THE FOLLOWING:  

  • the illegitimate use of materials in any form during a quiz or examination
  • copying answers from the quiz or examination paper of another student
  • plagiarizing (submitting as one's own ideas the work of another) or falsifying materials or information used in the completion of any assignment which is graded or evaluated as the student's individual effort
  • submitting the same work for more than one course without the consent of the instructors of each course in which the work is submitted
  • copying material from a web page and submitting it as one's own work
  • quoting extensively from a document without making proper references to the source

If  a student is found  committing  such acts in a quiz or  home assignment or exam or  term paper, he will be given a grade 0 in that part of the course.


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