COE 501 : Computer Architecture (3-0-3)
Spring Term 2007-08 (T072)
Section : 1
Day & Time
UT 5.00-6.15 P.M.
Location : 22/134
Catalog Description :
Classification of Computer Systems, architectural developments, computer performance, Linear and non-linear pipeline design, instruction and arithmetic pipeline, Superscalar processors, Memory hierarchy, cache and virtual memory, cache coherence, memory system performance, Parallel architectures, performance measures, SIMD and MIMD architectures, interconnection networks
The students are expected to carry out research projects in related field of studies.
Pre-requisite : COE 308 or Equivalent
Computer Architecture-A Quantitative Approach,
by J. L. Hennessy and D. A. Patterson, Morgan Kaufmann, Fourth Edition, 2006.
Course Objectives and Outcomes
· To understand performance measures used in computer design
- understand technology and cost trends in computer design
- understand how computer performance is measured and reported
- understand the quantitative principles that computer designers use
· To understand the principles of instruction set design
- study the statistics of instruction usage by programs executing on a recent instruction set architecture
- study the statistics of the use of memory addressing modes in programs executing on a recent instruction set architecture
- study the statistics of the types and sizes of operands used by programs executing on a recent instruction set architecture
- study in detail the encoding of instructions in a recent instruction set architecture
· To understand basic and advanced pipelining techniques
- understand basic methods for handling data, control, and resource hazards in single-pipeline processors
- analyze instruction-level parallelism (e.g., loop unrolling and detailed aspects of instruction dependence)
- analyze operation and performance of pipelines incorporating dynamic scheduling
- analyze operation and performance of pipelines incorporating dynamic branch prediction
- analyze operation and performance of pipelines incorporating multiple-instruction issue
· To understand advanced aspects of virtual memory and cache design.
- analyze cache timing and use that information in analyzing overall computer performance
- analyze implementation details of advanced cache features (e.g., write buffers, prefetch buffers, out-of-order fetches)
- analyze cache and TLB interaction and timing and use that information in analyzing overall computer system performance
· To understand Multiprocessor architectures and Thread Level Parallelism
- Understand the models for communication and memory architectures in multiprocessor systems
- Understand the basic methods for handling cache coherency problem in Symmetric shared-memory architectures (snooping protocols)
- Analyze the performance of Symmetric shared-memory multiprocessors
- Understand the basic methods for handling cache coherency problem in Distributed shared-memory architectures (Directory based protocols)
- Analyze the performance of Distributed shared-memory multiprocessors
- Analyze the synchronization mechanisms for multiprocessor systems
- Understand the basic principles of Multithreading - Thread Level Parallelism
- Analyze the operation and performance of interconnection networks
Tentative Grading Policy and Exam Dates:
Office Hours : Saturday, Sunday & Tuesday : 12.15 PM to 1.00 PM
Term Paper Guidelines
- Detailed Literature survey on the topic selected (related to Computer Architecture field)
- Preparation of the term paper
- Presentation of the paper
- Multi-core Processor Architectures
- Instruction & Data Level Parallelism
- Thread-level Parallelism
- Static & Dynamic Scheduling
- Static & Dynamic Branch Prediction
- Multi-level Caches
- Software Pipelining
- Storage Systems – SAN, NAS
- Interconnection Networks & Clusters
Because absence from class will prevent a student from getting the full benefit of a course, and because in many courses each student's involvement contributes to the learning process for all other students in the class, attendance is mandatory for every exercise of a course in which a student is registered. Excessive absences may result in withdrawal from the class.
A regular student should attend all classes and laboratory sessions. A student may be discontinued from a course and denied entrance to the final examination if his attendance is less than the limit determined by the University Council.
A regular student will not be allowed to continue in a course and to take the final examination and will be given a DN grade if his unexcused absences are more than 20% of the lecture and laboratory sessions scheduled for the course (Refer Undergraduate Bulletin – section on Attendance and withdrawal from study pp. 25-27 for more details).
Academic Dishonesty Policy
In order for instructors to fairly assess the quality and quantity of a student's learning (through course grades) as determined by work that students represent as their own, a relationship of trust between instructor and student is essential. Because violations of academic integrity most often involve, but are not limited to, efforts to deceive instructors, they represent a breach of the trust relationship between instructor and student, and undermine the core values of the university. For these reasons, the University and its instructors treat issues of academic dishonesty as serious violations of academic trust, and conduct rigorous investigations of students suspected of committing such acts.
ACTS OF ACADEMIC DISHONESTY INCLUDE, BUT ARE NOT LIMITED TO, THE FOLLOWING:
If a student is found committing such acts in a quiz or home assignment or exam or term paper, he will be given a grade 0 in that part of the course.