KFUPM - COMPUTER ENGINEERING DEPARTMENT

 

Online Lessons

COE 202 - Digital Logic Design

 

Dr. Alaaeldin Amin

Unit I

 

Number System and Codes

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1

Introduction. Information Processing, and representation. Digital vs Analog quantities.

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2

Number Systems. Binary, Octal and Hexadecimal #s

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3

Number System Arithmetic. Binary arith (Addition, Subtraction & Multiplication). Arith in other systems.

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4

Number base conversion (Dec to Bin, Oct, and Hex, General). Conv (Bin, OCT, Hex)

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5

Binary Storage & Registers. Signed Binary Number representation, Signed Mag, Rs &(R-1)s Complement

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6

Signed Binary Addition and Subtraction. Rs Complement. Signed Binary Addition and Subtraction. (R-1)s Complement

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7

Codes.  BCD, Excess-3, Parity Bits, ASCII & Uni-Codes

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Unit II

 

Binary Logic & Gates

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1

Binary logic and gates, Boolean Algebra, Basic identities of Boolean algebra. Algebraic manipulation, Complement of a function.

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2

Canonical and Standard forms, Minterms and Maxterms, Sum of products and Products of Sums.

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3

Physical properties of gates: fan-in, fan-out, propagation delay. Timing diagrams. Tri-state drivers.

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4

Map method of simplification: Two-, Three-, and Four-variable K-Map.

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5

Map manipulation: Essential prime implicants, Non-essential prime implicants, Simplification procedure, POS simplification, Dont care conditions and simplification, Five, and Six-variable K-Map.

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6

Universal gates; NAND, NOR gates: 2-level implementation. Multilevel Circuits.

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7

Exclusive-OR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking.

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Unit III

 

Combinational Logic

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1

Combinational Logic, Design Procedure & Examples.

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2

Half and Full Adders, Half and Full Subtractor, Ripple Carry Adder design and delay analysis

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3

Carry Look-Ahead Adder, Binary Adder-Subtractor. BCD Adder, Binary Multiplier

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4

MSI parts. Decoders, Decoder expansion,  combinational logic implementation using decoders, Encoders & Priority Encoders

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5

Multiplexers, Function Implementation using multiplexers, Demultiplexers

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6

Magnitude Comparator.

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7

Examples of MSI designs

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Unit IV

 

Sequential Circuits

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1

Sequential Circuits: Latches, Clocked latches: SR , D, T and JK. Race problem in clocked JK-Latch. Function & Excitation Tables of clocked latches: SR, D, and JK.

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2

Flip-Flops: Master-Slave, T-FF. Function & Excitation Tables of T-FF. Asynchronous/Direct Clear and Set Inputs. Setup, Hold

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3

Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables.

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4

Sequential Circuit Analysis: Input equations, State table.

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5

Mealy vs. Moore models of FSMs. Examples.

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Unit V

 

Registers & Counters

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1

Registers, Registers with parallel load, Shift Registers. Bi-directional shift register.

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2

Synchronous Binary Counters: Up-Down Counters.

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3

Counters with Parallel  load, enable, synchronous clear and asynchronous clear. Use of available counters to build counters of different count.

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4

Other counters: Ripple Counter, Arbitrary Count Sequence.

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Unit VI

 

Memory & PLDs

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1

Memory devices: RAMs & ROMs . Combinational Circuit Implementation with ROM

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2

Programmable Logic Devices: PLAs, PALs, FPGAa

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