COMPUTER ENGINEERING DEPARTMENT
COE 200 Fundamentals of
Computer Engineering
Online Lessons
Unit I 

Number System and Codes 

1 
Introduction. Information Processing, and representation. Digital vs Analog quantities. 

2 
Number Systems. Binary, Octal and Hexadecimal #’s 

3 
Number System Arithmetic. Binary arith (Addition, Subtraction & Multiplication). Arith in other systems. 

4 
Number base conversion (Dec to Bin, Oct, and Hex, General). Conv (Bin, OCT, Hex) 

5 
Binary Storage & Registers. Signed Binary Number representation, Signed Mag, R’s &(R1)’s Complement 

6 
Signed Binary Addition and Subtraction. R’s Complement. Signed Binary Addition and Subtraction. (R1)’s Complement 

7 
Codes. BCD, Excess3, Parity Bits, ASCII & UniCodes 

Unit II 

Binary Logic & Gates 

1 
Binary logic and gates, Boolean Algebra, Basic identities of Boolean algebra. Algebraic manipulation, Complement of a function. 

2 
Canonical and Standard forms, Minterms and Maxterms, Sum of products and Products of Sums. 

3 
Physical properties of gates: fanin, fanout, propagation delay. Timing diagrams. Tristate drivers. 

4 
Map method of simplification: Two, Three, and Fourvariable KMap. 

5 
Map manipulation: Essential prime implicants, Nonessential prime implicants, Simplification procedure, POS simplification, Don’t care conditions and simplification, Five, and Sixvariable KMap. 

6 
Universal gates; NAND, NOR gates: 2level implementation. Multilevel Circuits. 

7 
ExclusiveOR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation and checking. 

Unit III 

Combinational Logic 

1 
Combinational Logic, Design Procedure & Examples. 

2 
Half and Full Adders, Half and Full Subtractor Ripple Carry Adder design and delay analysis Binary Adders: 4Bit Ripple Carry Adder, 

3 
Carry LookAhead Adder, Binary AdderSubtractor. BCD Adder, Binary Multiplier 

4 
MSI parts. Decoders, Decoder expansion, combinational logic implementation using decoders, Encoders & Priority Encoders 

5 
Multiplexers, Function Implementation using multiplexers, Demultiplexers 

6 
Magnitude Comparator. 

7 
Examples of MSI designs 
Unit IV 

Sequential Circuits 

1 
Sequential Circuits: Latches, Clocked latches: SR , D, T and JK. Race problem in clocked JKLatch. Function & Excitation Tables of clocked latches: SR, D, and JK. 
2 
FlipFlops: MasterSlave, TFF. Function & Excitation Tables of TFF. Asynchronous/Direct Clear and Set Inputs. Setup, Hold 
3 
Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables. 
4 
Sequential Circuit Analysis: Input equations, State table. 
5 
Mealy vs. 
Unit V 

Registers & Counters 

1 
Registers, Registers with parallel load, Shift Registers. Bidirectional shift register. 
2 
Synchronous Binary Counters: UpDown Counters. 
3 
Counters with Parallel load, enable, synchronous clear and asynchronous clear. Use of available counters to build counters of different count. 
4 
Other counters: Ripple Counter, Arbitrary Count Sequence. 
Unit VI 

Memory & PLDs 

1 
Memory devices: RAMs & ROMs . Combinational Circuit Implementation with ROM 
2 
Programmable Logic Devices: PLAs, PALs, FPGA’a 