
A.A. Amin, “AreaEfficient HighSpeed Carry chain,” the IET
Electronics Letters, Volume 43, Issue 23, November 8 2007, pp. 12581260.

Adnan Gutub, Lahouari Ghouti, Alaaeldin Amin, Talal Alkharobi, and Mohammad K. Ibrahim, “Utilizing Extension
Character ‘Kashida’ With Pointed Letters For Arabic Text Digital
Watermarking”, International Conference on Security and Cryptography –
SECRYPT2007, Barcelona, Spain, July 28  31, 2007.

Alaaeldin Amin, “A HighSpeed SelfTimed CarrySkip Adder,”
IEE Proceedings  Circuits, Devices and Systems, Volume 153, Issue 6 ,
December 2006, pp. 574582.

Alaaeldin Amin, and Shinwari, M. W.
HighRadix MultiplierDividers: Theory, Design, and
Hardware,” under review for publication in the
IEEE Transaction on Computers Special section on Computer Arithmetic.

Turki F.
AlSomani and Alaaeldin Amin, “High Performance Elliptic Curve Scalar
Multiplication with Resistance against Power Analysis Attacks,”
under review for publication in the
IEICE Transactions on
Information and Systems.

Alaaeldin Amin, “Generalized Algorithms for Binary
Modulo Multiplication and MultiplicationDivision,”
in
preparation for submission to the IEEE Transaction
on VLSI.

Turki F.
AlSomani and Alaaeldin Amin, “Secure and Efficient Elliptic Curve
Cryptoprocessors,” in preparation for submission to the IEEE
Transaction on Computers.

T. AlSomani,
and A. Amin, “Hardware Implementations of GF(2^{m})
Arithmetic using Normal Basis,” Journal of Applied Sciences Vol. 6, No. 6,
2006, pp. 13621372.

Alaaeldin
Amin, “AreaDelay optimized Adders ,” in preparation for submission to
the IET Proceedings on Circuits, Systems and Devices

Alaaeldin
Amin, “Automatic Placement of Micropipeline Standard Cells,”
under review for publication in the Journal
of Circuits, Systems, and Computers.

M.
Mahmoud and Alaaeldin
Amin, “An
Asynchronous Modulo Multiplier for Cryptosystems,”
The 2^{nd} IEEEGCC
“Advancing
Technology in the GCC: Challenges and Solutions” NOVEMBER 2325,
2004, Manama, Bahrain.

Alaaeldin
Amin and Feras Maadi, “DoubleRail encoded SelfTimed Adder with Matched
delays”, The 10^{th} IEEE International Conference On Electronics,
Circuits And Systems (ICECS2003), December 1417, 2003, pp. 11721175.

Khaled M.
Elleithy and Alaa A. Amin "Area Estimation for DSP Algorithms", The 2000
IEEE Workshop on Signal Processing Systems (SiPS) Design and Implementation,
Lafayette, Louisiana, USA, October 11 – 13, 2000.

Adnan A.
A. Gutub and Alaaeldin A. M. Amin, ``An Expandable Montgomery Modular
Multiplication Processor``, Proceedings of the 1999 International Conference
on Microelectronics, pp 173176.

AlMulhem, A. S., Amin, A. A, and Youssef, H. “Stochastic Evolution
Algorithm for Technology Mapping,” Proceedings of the 8^{th}
Great Lakes Symposium on VLSI (GLS`98), Lafayette, Louisiana, Feb.
1998, pp. 380 – 385.

Amin,
A. A., Osman M. Y., AbdelAal, R. E., and AlMuhtaseb, H. "New Fault Models
and Efficient BIST Algorithm for Dual Port Memories," IEEE Trans. on CAD
of Integrated Circuits and Systems September 1997, pp. 9871000

Amin,
A., Hamzah, A., and AbdelAal, R. E., "A Generic DFT Approach for Pattern
Sensitive Faults in WordOriented Memories," IEE Proceedings on Computers
and Digital Techniques (pt. ~E), Vol. 143, No. 3, May 1996, pp. 199  203.

Elleithy, K. M. and Amin, A. A.., " Mapping CIRCALbased Algorithms to
Event Logic," Kuwait Journal of Science & Engineering, T1, pp. 27  42,
1996.

Amin,
A. A, and Elleithy, K. M. “SelfTiming of Event Logic DataPaths,” 1996
Int’l Conf. on Microelectronics (ICM’96), Cairo, pp. 111114, December
1618, 1996.

Amin,
A. and Brennan, J. “Electrically reprogrammable EPROM cell
with merged transistor and optimum area,”
US
Patent No. 5,455,793, October 3, 1995.

Elleithy, K. M. and Amin, A. A.., "An Event Logic Architecture for CIRCAL
Algorithms," the 7^{th}. IASTED International Conference on
Parallel and Distributed Computing and Systems, Georgetown University,
Washington, D.C., pp. 311313, October 1821 1995.

Amin,
A. A, Elleithy, K. M., and Hassan, M. “A Standard Cell Library for
Asynchronous Event Logic,”, 1995 Int’l Conf. on Microelectronics
(ICM’95), December 1820, 1995.

Raffed, B., Amin, A. and Youssef, H., M. “The Architecture of a
SelfTimed/Synchronous FPGA,”, 1995 Int’l Conf. on Microelectronics
(ICM’95), December 1820, 1995.

Elleithy, K. M., and Amin, A. A., “Synthesizing Digital Signal Processing
Algorithms from Formal Descriptions,”, 6^{th} Int’l Conf.
on Signal Processing Applications and Technology (ICSPAT95), Boston,
pp. 901905, Oc. 2426, 1995.

Elleithy, K. M. and Amin, A. A. "A Formal Approach for Synthesizing Digital
Signal Processing Algorithms," IEEE Singapore International Conference on
Signal Processing, Circuits and Systems, Singapore, July 37, 1995.

Amin,
A. and Brennan, J. “Electrically reprogrammable EPROM cell
with merged transistor and optimum area,”
US Patent No. 5,293,328, March 8, 1994

Elleithy, K. M. and Amin, A. A. "A Formal Verification of DSP VLSI
Architectures: A Tutorial," 37th Midwest Symposium on Circuits and Systems,
Lafayette, Louisiana, August, 1994, pp. 351355.

Elleithy, K. M., and Amin, A. A., “Parallelism Analysis and Extraction of
Digital Signal Processing Algorithms,”, 28^{th} Asilomar
Conf. on Signals, Systems, and Computers, Oct. 31  Nov. 2, 1994,
Pacific Grove, Calif., pp. 1041  1045.

Amin,
A. A., Osman M. Y., AbdelAal, R. E., and AlMuhtaseb, H. "Efficient O()
BIST Algorithm for DDNPS Faults in Dual Port Memories," IEEE 1994
International Test Conference (ITC94), October 2  6, 1994,
Washington, D.C., pp. 850  859.

Elleithy, K. M., and Amin, A. A., “A Characteristic Model for Formal
Parallel Hardware Description Languages,” Workshop on Optimization and
Parallel Computation, AlAin, United Arab Emirates, May, 1994.

Amin,
A. and Emoto, Bernard "A High Speed Sense Amplifier for EPROM Single
Transistor Memory Cell," US Patent No. 5,117,394, May 26, 1992

Amin,
A, " A SpeedOptimized Array Architecture for Flash EEPROMS," IEE
Proceedings on Circuits, Devices and Systems (pt. ~G), vol. 140, No. 3, June
1993, pp. 177  181.

Amin,
A., " Design and Analysis of a High Speed Sense Amplifier for Single
Transistor NonVolatile Memory Cells," IEE Proceedings on Circuits, Devices
and Systems (pt. ~G), vol. 140, No. 2, April 1993, pp. 117  122.

Amin
A., "Design, Selection and Implementation of Flash Erase EEPROM Memory Cell
Structures," IEE Proceedings on Circuits, Devices and Systems (pt. ~G), Vol.
139, No. 3, June 1992, pp. 370376.

Belal, R. and Youssef, H., Amin, A. " An Interconnection Model for
IslandStyle FPGAs," ICM'93, The International Conference on
Microelectronics, Dhahran, Saudi Arabia, December1993, pp. 202  205.

Amin,
A., Belal, R. and Youssef, H. " A New Nonvolatile Reprogrammable FPGA
Architecture," ICM'92, The International Conference on
Microelectronics, Tunisia, December1992, pp. 4.1.3.1  4.1.3.4.

Raffed, B., Amin, A. and Youssef, H. "Trends and Issues in FPGA
Architectures for ASIC Design,", 13th National Computer Conference,
Riyadh (NCC'13), pp. 394412, Nov 1992.

Amin,
A. "A Novel Architecture for Flash Erase EPROM Memory," US. Patent
No. 4,999,812, March 1991

Amin,
A., AbdelAal, R. E. and Osman, M. Y., " The Design and Architecture of a
Histogrammer Memory Chip," ICM'91, The International Conference on
Microelectronics, December 1991, pp. 177  180.

Amin,
A., " A Novel Flash Erase EEPROM Memory Cell with reversed Poly Roles,"
IEEE Melecon'91, Med. Electrotech. Conf, May 1991, pp. 311  314.

Amin,
A. and Aref, M., " An Intelligent EPROM Silicon Compiler," IEEE
Pacific RIM Conference, May 1991, Victoria, Canada, pp. 357  359.

Amin,
A., " A Novel Double Poly Flash Erase EEPROM Memory Cell," ICM'90,
The International Conference on Microelectronics, October 1990, pp.
2.15.1  2.15.4.

Amin,
A., " A Novel Flash Erase EEPROM Memory Cell with Asperities Aided Erase,"
ESSDERC'90, 20th. European Solid State Device Research
Conference , September 1990, pp. 177180.

Amin,
A. and Smith, K. F., "Test Generation and Fault Detection of VLSI PPL
Circuits," INTEGRATION, The VLSI Journal, 7(3), pp. 303324, 1989.

Amin, Alaaeldin, "Design, Analysis, and FPGA
prototyping of HighPerformance Arithmetic for Cryptographic Applications,"
Technical Reports # 14, KACST Project Number AR2217,
Ramadhan 1424 – Safar 1425.

AlSomani Turki F, and Amin, Alaaeldin, "Hardware
Implementations of GF(2^m) Arithmetic using Normal Basis" CCSE Technical
Report KFUPMCCSE2005006/COE.

AbdelBarr, Mostafa, Amin, Alaaeldin, and AlSomani
Turki F."Design, Analysis, and FPGA prototyping of HighPerformance
Arithmetic for Cryptographic Applications: Literature
ReviewPart 1:Cryptographic Algorithms," CCSE Technical Report
KFUPMCCSE2004001/COE.

AbdelBarr, Mostafa, Amin, Alaaeldin, and AlSomani
Turki F. "Design, Analysis, and FPGA prototyping of HighPerformance
Arithmetic for Cryptographic Applications: Literature
ReviewPart 2:Cryptographic Algorithms," CCSE Technical Report
KFUPMCCSE2004002/COE.

Amin
and H. Youssef, "The
design
and
development
of a new family nonvolatile
SRAMBased Field Programmable Gate Arrays
(FPGAs),"
KACST project
report # ( AR1467 ),
July
1998.

M.
Elleithy, and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm
Design," KACST project report # (AR1311),
Rajab 1417.

Amin,
A. A., Osman M. Y., AbdelAal, R. E., and AlMuhtaseb, H. "An O()
BIST Algorithm for Detection of Duplex Dynamic Pattern Sensitive Faults in
Dual Port Memories," KFUPM CCSE Tech Report 015, July 10, 1993.