1. A.A. Amin, “Area-Efficient High-Speed Carry chain,” the IET Electronics Letters, Volume 43, Issue 23, November 8 2007, pp. 1258-1260.
  2. Adnan Gutub, Lahouari Ghouti, Alaaeldin Amin, Talal Alkharobi, and Mohammad K. Ibrahim, “Utilizing Extension Character ‘Kashida’ With Pointed Letters For Arabic Text Digital Watermarking”, International Conference on Security and Cryptography – SECRYPT-2007, Barcelona, Spain, July 28 - 31, 2007.
  3. Alaaeldin Amin, “A High-Speed Self-Timed Carry-Skip Adder,” IEE Proceedings - Circuits, Devices and Systems, Volume 153, Issue 6 , December 2006, pp. 574-582.
  4. Alaaeldin Amin, and  Shinwari, M. W. High-Radix Multiplier-Dividers: Theory, Design, and Hardware,” under review for publication in the IEEE Transaction on Computers- Special section on Computer Arithmetic.
  5. Turki F. Al-Somani and Alaaeldin Amin, “High Performance Elliptic Curve Scalar Multiplication with Resistance against Power Analysis Attacks,”  under review for publication in the IEICE Transactions on Information and Systems.
  6. Alaaeldin Amin, “Generalized Algorithms for Binary Modulo Multiplication and Multiplication-Division,” in preparation for submission to the IEEE Transaction on VLSI.
  7. Turki F. Al-Somani and Alaaeldin Amin, “Secure and Efficient Elliptic Curve Cryptoprocessors,”  in preparation for submission to the IEEE  Transaction on Computers.
  8. T. Al-Somani, and A. Amin, “Hardware Implementations of GF(2m) Arithmetic using Normal Basis,” Journal of Applied Sciences Vol. 6, No. 6, 2006, pp. 1362-1372.
  9. Alaaeldin Amin, “Area-Delay optimized Adders ,”  in preparation for submission to the IET Proceedings on Circuits, Systems and Devices
  10. Alaaeldin Amin, “Automatic Placement of Micropipeline Standard Cells,” under review for publication in the Journal of Circuits, Systems, and Computers.
  11. M. Mahmoud and Alaaeldin Amin, “An Asynchronous Modulo Multiplier for Cryptosystems,” The 2nd IEEEGCC Advancing Technology in the GCC: Challenges and Solutions” NOVEMBER 23-25, 2004, Manama, Bahrain.
  12. Alaaeldin Amin and Feras Maadi, “Double-Rail encoded Self-Timed Adder with Matched delays”, The 10th IEEE International Conference On Electronics, Circuits And Systems (ICECS2003), December 14-17, 2003, pp. 1172-1175.
  13. Khaled M. Elleithy and Alaa A. Amin "Area Estimation for DSP Algorithms", The 2000 IEEE Workshop on Signal Processing Systems (SiPS) Design and Implementation, Lafayette, Louisiana, USA, October 11 – 13, 2000.
  14. Adnan A. A. Gutub and Alaaeldin A. M. Amin, ``An Expandable Montgomery Modular Multiplication Processor``, Proceedings of the 1999 International Conference on Microelectronics, pp 173-176.
  15. Al-Mulhem, A. S., Amin, A. A, and Youssef, H. “Stochastic Evolution Algorithm for Technology Mapping,” Proceedings of the 8th Great Lakes Symposium on VLSI  (GLS`98), Lafayette, Louisiana, Feb. 1998, pp. 380 – 385.
  16. Amin, A. A., Osman M. Y., Abdel-Aal, R. E., and Al-Muhtaseb, H. "New Fault Models and Efficient BIST Algorithm for Dual Port Memories," IEEE Trans. on CAD of Integrated Circuits and Systems September 1997, pp. 987-1000
  17. Amin, A., Hamzah, A., and Abdel-Aal, R. E.,  "A Generic DFT Approach for Pattern Sensitive Faults in Word-Oriented Memories," IEE Proceedings on Computers and Digital Techniques (pt. ~E), Vol. 143, No. 3,  May 1996, pp. 199 - 203.
  18. Elleithy, K. M.  and Amin, A. A..,  " Mapping  CIRCAL-based Algorithms to Event Logic," Kuwait Journal of  Science & Engineering, T1, pp. 27 - 42, 1996.
  19. Amin, A. A, and Elleithy, K. M. “Self-Timing of Event Logic Data-Paths,” 1996 Int’l Conf. on Microelectronics (ICM’96), Cairo, pp. 111-114, December 16-18, 1996.
  20. Amin, A. and Brennan, J. “Electrically reprogrammable EPROM cell with merged transistor and optimum area,” US Patent  No. 5,455,793,  October 3, 1995.
  21. Elleithy, K. M.  and Amin, A. A..,  "An Event Logic Architecture for CIRCAL Algorithms," the 7th. IASTED International Conference on Parallel and Distributed Computing and Systems, Georgetown University, Washington, D.C., pp. 311-313, October 18-21 1995.
  22. Amin, A. A, Elleithy, K. M., and Hassan, M. “A Standard Cell Library for Asynchronous Event Logic,”, 1995 Int’l Conf. on Microelectronics (ICM’95), December 18-20, 1995.
  23. Raffed, B., Amin, A. and Youssef, H., M. “The Architecture of a Self-Timed/Synchronous FPGA,”, 1995 Int’l Conf. on Microelectronics (ICM’95), December 18-20, 1995.
  24. Elleithy, K. M., and Amin, A. A., “Synthesizing Digital Signal Processing Algorithms from Formal Descriptions,”, 6th Int’l Conf. on Signal Processing Applications and Technology (ICSPAT-95), Boston, pp. 901-905, Oc. 24-26, 1995.
  25. Elleithy, K. M. and Amin, A. A. "A Formal Approach for Synthesizing Digital Signal Processing Algorithms,"  IEEE Singapore International Conference on Signal Processing, Circuits and Systems, Singapore,  July  3-7, 1995.
  26. Amin, A. and Brennan, J. “Electrically reprogrammable EPROM cell with merged transistor and optimum area,” US Patent  No. 5,293,328,  March 8, 1994
  27. Elleithy, K. M. and Amin, A. A. "A Formal Verification of DSP VLSI Architectures: A Tutorial," 37th Midwest Symposium on Circuits and Systems, Lafayette, Louisiana,  August, 1994, pp. 351-355.
  28. Elleithy, K. M., and Amin, A. A., “Parallelism Analysis and Extraction of Digital Signal Processing Algorithms,”, 28th Asilomar Conf. on Signals, Systems, and Computers, Oct. 31 - Nov. 2, 1994, Pacific Grove, Calif., pp. 1041 - 1045.
  29. Amin, A. A., Osman M. Y., Abdel-Aal, R. E., and Al-Muhtaseb, H. "Efficient O() BIST Algorithm for DDNPS Faults in Dual Port Memories," IEEE 1994 International Test Conference (ITC-94), October 2 - 6, 1994, Washington, D.C., pp. 850 - 859.
  30. Elleithy, K. M., and Amin, A. A., “A Characteristic Model for Formal Parallel Hardware Description Languages,” Workshop on Optimization and Parallel Computation, Al-Ain, United Arab Emirates, May, 1994.
  31. Amin, A. and Emoto, Bernard "A High Speed Sense Amplifier for EPROM Single Transistor Memory Cell," US Patent  No. 5,117,394,  May 26, 1992
  32. Amin, A, " A Speed-Optimized Array Architecture for Flash EEPROMS," IEE Proceedings on Circuits, Devices and Systems (pt. ~G), vol. 140, No. 3, June 1993, pp. 177 - 181.
  33. Amin, A., " Design and Analysis of a High Speed Sense Amplifier for Single Transistor Non-Volatile Memory Cells," IEE Proceedings on Circuits, Devices and Systems (pt. ~G), vol. 140, No. 2, April 1993, pp. 117 - 122.
  34. Amin A., "Design, Selection and Implementation of Flash Erase EEPROM Memory Cell Structures," IEE Proceedings on Circuits, Devices and Systems (pt. ~G), Vol. 139, No. 3, June 1992, pp. 370-376.
  35. Belal, R. and Youssef, H., Amin, A. " An Interconnection Model for Island-Style FPGAs," ICM'93, The International  Conference on Microelectronics, Dhahran, Saudi Arabia, December1993, pp. 202 - 205.
  36. Amin, A., Belal, R. and Youssef, H. " A New Nonvolatile Reprogrammable FPGA Architecture," ICM'92, The International  Conference on Microelectronics, Tunisia, December1992, pp. 4.1.3.1 - 4.1.3.4.
  37. Raffed, B., Amin, A. and Youssef, H. "Trends and Issues in FPGA Architectures for ASIC Design,", 13th National Computer Conference, Riyadh (NCC'13), pp. 394-412, Nov 1992.
  38. Amin, A. "A Novel Architecture for Flash Erase EPROM  Memory," US. Patent No. 4,999,812, March 1991
  39. Amin, A.,  Abdel-Aal, R. E. and Osman, M. Y., " The Design and Architecture of a Histogrammer Memory Chip," ICM'91, The International Conference on Microelectronics, December 1991, pp. 177 - 180.
  40. Amin, A., " A Novel Flash Erase EEPROM Memory Cell with reversed Poly Roles," IEEE Melecon'91, Med. Electrotech. Conf, May 1991, pp. 311 - 314.
  41. Amin, A. and Aref, M., " An Intelligent EPROM Silicon Compiler," IEEE Pacific RIM Conference, May 1991, Victoria, Canada, pp. 357 - 359.
  42. Amin, A., " A Novel Double Poly Flash Erase EEPROM Memory Cell," ICM'90, The International  Conference on Microelectronics, October 1990, pp. 2.15.1 - 2.15.4.
  43. Amin, A., " A Novel Flash Erase EEPROM Memory Cell with Asperities Aided Erase," ESSDERC'90, 20th. European Solid State Device Research Conference , September 1990, pp. 177-180.
  44. Amin, A. and Smith, K. F., "Test Generation and Fault Detection of VLSI PPL Circuits," INTEGRATION, The VLSI Journal, 7(3), pp. 303-324, 1989.
  45. Amin, Alaaeldin, "Design, Analysis, and FPGA prototyping of High-Performance Arithmetic for Cryptographic Applications," Technical  Reports # 1-4, KACST Project Number AR-22-17, Ramadhan 1424 – Safar 1425.
  46. Al-Somani Turki F, and Amin, Alaaeldin, "Hardware Implementations of GF(2^m) Arithmetic using Normal Basis" CCSE Technical Report KFUPM-CCSE-2005-006/COE.
  47. Abdel-Barr, Mostafa, Amin, Alaaeldin, and Al-Somani Turki F."Design, Analysis, and FPGA prototyping of High-Performance Arithmetic for Cryptographic Applications: Literature Review-Part 1:Cryptographic Algorithms," CCSE Technical Report KFUPM-CCSE-2004-001/COE.
  48. Abdel-Barr, Mostafa, Amin, Alaaeldin, and Al-Somani Turki F. "Design, Analysis, and FPGA prototyping of High-Performance Arithmetic for Cryptographic Applications: Literature Review-Part 2:Cryptographic Algorithms," CCSE Technical Report KFUPM-CCSE-2004-002/COE.
  49. Amin and H. Youssef, "The design and development of a new family nonvolatile SRAM-Based Field Programmable Gate Arrays (FPGAs)," KACST project report # ( AR-14-67 ), July 1998.
  50. M. Elleithy, and A. A. Amin, "A Formal Methodology for Parallel VLSI Algorithm Design," KACST project report # (AR-13-11), Rajab 1417.
  51. Amin, A. A., Osman M. Y., Abdel-Aal, R. E., and Al-Muhtaseb, H. "An O() BIST Algorithm for Detection of Duplex Dynamic Pattern Sensitive Faults in Dual Port Memories,"  KFUPM CCSE Tech Report 015, July 10, 1993.

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