8 years of industrial experience at National Semiconductor Corporation, a large and leading multi-national Integrated Circuit manufacturer with headquarters in Santa Clara California (Silicon Valley).
Wide experience in the field of VLSI Integrated Circuit design in general and in MOS Memory Design in particular.
Have been involved in all phases of the design cycle of VLSI Integrated Circuits, including product performance specification, process technology definition, circuit design and layout, logic and device level simulation, test requirements, circuit debugging and troubleshooting as well as final testing.

Projects Accomplished

Worked on the following projects as a member/leader of the design team:

* Design of 32K CMOS EPROM,
* Design of 64K NMOS EPROM,
* Design of 256K NMOS DRAM,
* Design of 256K CMOS EPROM, (Project leader)
* Design of 1MB EPROM, and (Project leader)
* Design of 256K CMOS FLASH EEPROM (Project Leader)

Patents

"A High Speed Sense Amplifier for EPROM Single Transistor Memory Cell," US Patent No. 5,117,394, May 26, 1992; European Patent No. 89121444.7-, December 1989.
"A Novel Architecture for Flash Erase EPROM Memory," US. Patent No. 4,999,812, March 1991; European Patent No. 89121391.0-, December 1989.
"A New Electrically Reprogrammable EPROM Cell with Merged Transistor and Optimum Area," European Patent No. 2310776.7-, February 1993.

Design & Modeling of VLSI Circuits / Systems, Digital System Testing & Design for testability, ASIC field programmable VLSI Technology, ASIC memory design and memory testing, Asynchronous VLSI system Design, Design automation and computer architecture.

ACADEMIC / TECHNICAL INFORMATION:

Industrial Experience

Projects Accomplished

Dr. Alaaeldin Amin

Patents

Research Interests