KFUPM - COMPUTER ENGINEERING DEPARTMENT

 

COE 405 (3-0-3)

Design and Modeling of Digital Systems

 

Catalog Description

Mastering the hardware description language, VHDL, for the design (specification, simulation, and synthesis) of digital systems using programmable logic or VLSI components. Designing complete digital systems starting from the concept, advancing through the simulation, synthesis, and test, by using different styles in VHDL, namely structural, dataflow, and behavioral, for describing the architecture.

Instructor

 Dr. Alaaeldin Amin

Room  22-314

Phone: 2862

e-mail:    amindin@kfupm

 

Text Book :   Zainalabedin Navabi, “VHDL: Analysis and Modeling of Digital Systems”, McGraw-Hill, Inc., 2nd edition, 1997.

 

Lecture Notes  

*

 

Course Topics           

 

 

Topic

 

Reference

1.      

Structured Design Methodologies

Digital System Design, Abstraction hierarchy, Types of Behavioral Descriptions The Digital Design Space & Design Decomposition.

Handout, Ch 1

2.      

VHDL Quick Overview

Design Partitioning & Top-Down Design. Design Entities, Signals vs. Variables, Architectural Bodies, Different design views, behavioral model, dataflow model, structural models.

Handout, Ch 3

3.      

Digital System Design

Data Path and Control Path. Sample designs. VHDL Models

Handout

4.      

Design & Modeling Tools

Tutorials on available Simulators

 

5.      

VHDL Language Basics

Lexical Elements, Data Types  (Scalars & Composites), Type Conversion, Attributes, Classes of objects.  Operators & Precedence, Overloading.

Handout, Ch. 7

6.      

Signals, Delays & Concurrency.

Variables vs. Signals, sequential vs concurrent constructs, Signal Propagation Delay & Delay types, Transactions, Events and Transaction Scheduling, Signal Attributes.

Ch 4, handout

7.      

Structural Models

Structural Models, Configuration Statement, Modeling Iterative/Regular Structures, and Test Benches.

Ch 5

8.      

Design Organization & Parameterization

Packages & Libraries. Design Parameterization, Design Configuration & General purpose test bench.

Ch 6

9.      

Dataflow Models

Concurrent Signal Assignment, Block statements, Guards, Resolution functions, Resolved Signals and Signal Kinds, Data Flow Moore & Mealy Models, Data & Control Path Data Flow Models.

Ch 8

10.  

Behavioral Models

Process & Wait Statements, Assert Statement, General Algorithmic Model, Moore and Mealy Machine Algorithmic Models, Data & Control Path Design.

Ch. 9

11.  

Introduction to VHDL  Synthesis

Combinational, sequential logic synthesis, state machine synthesis.

Handout Notes App. C.

12.  

CPU Design Example

 

Ch10, 11.