KFUPM - COMPUTER ENGINEERING DEPARTMENT

 

Principles of VLSI Design COE 360 (3-0-3)

Course Description

 

Instructor

 

Dr. Alaaeldin Amin,

Room 22-314

Phone: 2862

e-mail: amin@ccse

 

Sat: 10:00 10:50 Mon: 10:00 11:45 Tue:10:55 11:45 OR: By Appointment

Catalog Description

MOS Transistor operation and limitations, MOS digital logic circuits (NMOS & CMOS), static & dynamic logic, combinational and sequential circuits, propagation delay, transistor sizing, MOS IC fabrication, layout and design rules, stick diagrams, IC Design and Verification Tools, subsystem design and case studies, and practical considerations.

Prerequisite: EE 203

Text Book: S. Kang and Y. Leblebici, ``CMOS Digital Integrated Circuits: Analysis and design``, McGraw-Hill, second Edition, 1999.

Course Learning Outcome:

Outcome 1: Ability to apply knowledge of mathematics, science, and engineering in the design, analysis and modeling of digital integrated circuits [ABET Criterion 3a]

Outcome 2: Ability to design and conduct experiments using SPICE to characterize and optimize digital integrated circuits [ABET Criterion 3b]

Outcome 3: Ability to Design, Verify, Analyze and Evaluate the performance (speed, Power, Area, Noise margins) of different MOS digital integrated circuits for different design specifications [ABET Criterion 3c]

Outcome 4: Ability to use CAD tools in the design and verification of digital integrated circuits [ABET Criterion 3k]

Outcome 5: Ability to function as an effective team member [ABET Criterion 3d]

Outcome 6: Ability to document and communicate design efforts effectively using written reports [ABET Criterion 3g]

Topics:

1.                Review Material: Semiconductor types and doping, Mobility and Conductivity. Mass-action-Law, Charge-Neutrality-Law. Drift and Diffusion currents in semiconductors, P-N junction, built-in Potential, Transition Capacitance, and breakdown voltage. Basic Specifications of Digital Circuits (VOL, VOH, VIL , VIH, IOL, IOH, IIL, IIH, Noise Margin, Fan-in, Fanout and loading, Power dissipation). MOS Transistor Structure, Theory of Operation, and IV characteristics. SPICE simulations.

 

2.                The MOS Transistor: Body effect, pass transistors, transmission gates.

 

3.                MOS Static Logic. CMOS logic, Tri-State Drivers, inverter delay models, transistor sizing, MOS capacitances and power dissipation in MOS circuits. Cascade Voltage Switch Logic (CVSL), Latches and registers.

 

4.                CMOS Dynamic & Other Logic: Dynamic CMOS Logic (Precharge/Evaluate), Charge Sharing, Domino logic, NORA CMOS logic, True Single-Phase Clock (TSPC) logic.

 

5.                Ratiod Logic: NMOS and Pseudo-Static CMOS logic, Pass Transistor logic.

 

6.                CMOS Subsystem Design & Case Studies (Term Project). {e.g., Design of CLA Adder, shifter, ALU, decoders, counters, SRAM cells, case studies}.

 

7.                CMOS Processing Technology, Photolithography, masking and etching. CMOS fabrication. CMOS design rules and layout. CMOS Latchup. Sheet resistance, integrated resistors, and capacitors. Distributed RC Effect.

 

8.                Second-Order Considerations. MOS transistor Scaling, Small geometry & second order effects.

 

9.                VLSI Design Styles. Custom vs Semi-custom techniques, Standard Cells, Gate Arrays, and FPGAs