Research

Ahmad is involved in research in VLSI design and test, design-for-testability, built-in self-test, nanotechnology electronics reliability, computer-aided design automation,  iterative heuristics and their parallelization for VLSI design,  and reliable computing. Publications below reflect the extent of involvement in each area.

MS theses committees:

1. Mustafa Imran, “Test Data Volume Reduction of Scan-Based Deterministic Test based on Scan Chains Compatibility using Partitioning & Relaxation,” M.Sc. Thesis, King Fahd University of Petroleum and Minerals, 2007 (Member).

2. Ali Zaidi, “An efficient reconfigurable archetecture for secret and public key cryptography,” M.Sc. Thesis, King Fahd University of Petroleum and Minerals, 2007 (Member).

Funded Projects:

1. “Scan Test Cost and Power Reduction through Systematic Scan Reconfiguration,” KFUPM funded project, 2006-2007 (Primary Investigator).

2. “Test Data Volume Reduction of Scan-Based Deterministic Test based on Scan Chains Compatibility using Partitioning & Relaxation,” Sabic funded project, 2006-2007 (Co-Investigator).

3. “Energy-Delay Efficient Test,” BAE, British Council, and KFUPM funded project, 2006 (Primary Investigator).

Publications:

THESES:

1. Ahmad Al-Yamani, “A Parallel Tabu Search Algorithm for VLSI Standard Cell Placement,” M.Sc. Thesis, King Fahd University of Petroleum and Minerals, June 1999.

2. Ahmad Al-Yamani, “Deterministic Built-In Self Test for Digital Circuits,” Ph.D. Thesis, Stanford University, April 2004. (ppt)

JOURNALS:

3. Al-Yamani, A.A., S. Sait and H. Youssef, "Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations," Journal of Heuristics on Parallel Metaheuristics, 8(3), pp. 277-304, May 2002.

4. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Optimized Reseeding by Seed Ordering and Encoding," IEEE Transactions on Computer-Aided Design (TCAD'05), 24(2), pp. 264-271, February 2005.

5. Al-Yamani, A.A, and E.J. McCluskey, “Test Chip Experimental Results on High Level Structural TestACM Transactions on Design Automation of Electronic Systems (TODAES’05), October 2005. (Invited)

6. Al-Yamani, A., N. Devta-Prasanna, E. Chmelar, M. Grinchuk, and A. Gunda, “Scan Test Cost and Power Reduction through Systematic Scan Reconfiguration,” Accepted for IEEE Transactions on Computer-Aided Design, to appear in 2007.

CONFERENCES AND SYMPOSIA:

7. S. Sait, Youssef, Barada, and A. Al-Yamani, "A Parallel Tabu Search Algorithm for VLSI Standard Cell Placement," IEEE International Symposium on Circuits and Systems (ISCAS'00), Geneva, Switzerland, May 2000.

8. Al-Yamani, A.A., N. Oh, and E.J. McCluskey, "Algorithm-Based Fault Tolerance: A Performance Perspective Based on Error Rate," Fast Abstract, IEEE International Symposium on Dependable Systems and Networks (DSN'01), Gotenberg, Sweden, July 1-4, 2001.  (ppt)

9. Al-Yamani, A.A., N. Oh, and E.J. McCluskey,"Performance Evaluation of Checksum-Based ABFT," 16th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), San Francisco, CA, Oct. 24-26, 2001. (ppt)

10. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Techniques for Testing Digital Circuits with Constraints," 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02), Vancouver, BC, Canada, Nov. 6-8, 2002. (ppt)

11. Al-Yamani, A.A., S. Sait and H. Barada, "HPTS: Heterogeneous Parallel Tabu Search for VLSI Placement," IEEE Congress on Evolutionary Computing (CEC'02), Honolulu, Hawaii, May 12-17, 2002.

12. Al-Yamani, A.A., S. Sait, H. Youssef, and H. Barada, "Parallel Tabu Search in a Heterogeneous Environment," IEEE International Parallel and Distributed Processing Symposium (IPDPS'03), Nice, France, Apr. 22-26, 2003.

13. Al-Yamani, A.A., and E.J. McCluskey, "Built-In Reseeding for Serial BIST," 21st IEEE VLSI Test Symposium (VTS'03), Napa Valley, CA, Apr. 27-May 1, 2003. (ppt)

14. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "BIST Reseeding with Very Few Seeds," 21st IEEE VLSI Test Symposium (VTS'03), Napa Valley, CA, Apr. 27-May 1, 2003. (ppt)

15. Al-Yamani, A.A., and E.J. McCluskey, "Seed Encoding for LFSRs and Cellular Automata," 40th ACM/IEEE Design Automation Conference (DAC'03), Anaheim, CA, June 2-6, 2003. (ppt)

16. McCluskey, E.J., A. A. Al-Yamani, C.-M. Li, C.W. Tseng, E. Volkerink, F. Ferhani, E. Li, and S. Mitra,"ELF-Murphy Data on Defects and Test Sets," 22nd IEEE VLSI Test Symposium (VTS’04), Napa Valley, CA, Apr. 25-28, 2004. (ppt)

17. Salama, K.N., and A.A. Al-Yamani, " Analysis of Self-Correcting Active Pixel Sensors," SPIE's 17th Annual Symposium on Electronic Imaging Science and Technology, San Jose, CA, January 2005.

18. Al-Yamani, A.A., and E.J. McCluskey, "BIST-Guided ATPG," 6th IEEE International Symposium on Quality Electronics Design (ISQED'05), San Jose, CA, March 21-23, 2005. (ppt)

19. Al-Yamani, A.A., Erik Chmelar and Mikhail Grinchuk, "Segmented Addressable Scan Architecture," 23rd IEEE VLSI Test Symposium (VTS'05), Palm Springs, CA, May 1-5, 2005. (ppt)

20. Park, I., A. Al-Yamani, and E.J. McCluskey, “Effective TARO Pattern Generation23rd IEEE VLSI Test Symposium (VTS'05), Palm Springs, CA, May 1-5, 2005. (ppt)

21. Al-Yamani, A.A., N. Devta-Prasanna, and A. Gunda, “Should Illinois-Scan Architectures be Centralized or Distributed?IEEE International Symposium on Defect and Fault Tolerance (DFT’05), Monterey, CA, Oct 3-5, 05. (ppt)

22. Al-Yamani, A “DFT for Controlled-Impedance IO Buffers43rd ACM/IEEE Design Automation Conference (DAC'06), San Francisco, CA, July 24-26, 2006. (ppt)

23. Al-Yamani, A., N. Devta-Prasanna, and A. Gunda, “Systematic Scan Reconfiguration12th IEEE Asia and South Pacific Design Automation Conference (ASPDAC'07), Yokohama, Japan, Jan 23-26, 2007. (ppt)

24. Ramsundar, S., A Al-Yamani and D. Pradhan, “Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm, ” IEEE International Symposium on Quality Electronics Design (ISQED'07), San Jose, CA, March 26-28, 2007.

25. El-Maleh, A., B. Al-Hashimi, and A. Al-Yamani, “N2-Transistor Structure for Defect-Tolerance at the Nanoscale,” IEEE Eurpean Test Symposium (ETS'07), Freiburg, Germany, May 20-24, 2007.

WORKSHOPS:

26. Al-Yamani, A.A., and E.J. McCluskey, "Low-Overhead Built-In BIST Reseeding," 3rd IEEE International Workshop on Test Resource Partitioning (TRP'02), Baltimore, MD, Oct. 10-11, 2002. (ppt)

27. Al-Yamani, A.A., and E.J. McCluskey, "Test Quality for High Level Structural Test," IEEE High Level Design Validation and Test (HLDVT'04), Sonoma, CA, November 2004. (ppt)

28. Al-Yamani, A.A., "Test Time Reduction through Power Control," IEEE International Design and Test (IDT'06), Dubai, UAE, November 2006. (ppt)

29. Argyrides, C, J. Mathew, A. Al-Yamani, and D. Pradhan, " Performance Analysis of an Error Tolerant Low Power Memory Architecture," IEEE International Design and Test (IDT'06), Dubai, UAE, November 2006.

30. Argyrides, C, D Pradhan, and A Al-Yamani, "Non-square Meshes for Improved Yield in Nanotechnology Circuits," IEEE Latin-American Test Workshop (LATW07), Cuzco, Peru, March 2007.

31. El-Maleh, A., B. Al-Hashimi, and A. Al-Yamani, “Defect-Tolerant N2-Transistor Structure for Reliable Design at the Nanoscale, ” IEEE Workshop on Robust Computing with Nano-scale Devices: Progresses and Challenges, Nice, France, Apr 16-20, 2007.

TECHNICAL REPORTS:

32. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Avoiding Illegal States in Pseudorandom Testing of Digital Circuits," Stanford CRC TR 02-02.

33. Al-Yamani, A.A., and E.J. McCluskey, "Built-In Reseeding for Built-In Self Test," Stanford CRC TR 02-03.

PATENTS:

34. Grinchuk, M., A. A. Al-Yamani, and E. Chmelar, "System And Method For Implementing Postponed Quasi-Masking Test Output Compression In Integrated Circuit," Filed with USPTO, Dec 16, 2004, Application number 20060156128.

35. Al-Yamani, A. A., M. Grinchuk, and E. Chmelar, "Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits," Filed with USPTO, March 31, 2005, Application number 20060236176.

36. Al-Yamani, A. A., N. Devta-Prasanna, and A. Gunda, "Systematic Scan Reconfiguration," Filed with USPTO, April 26, 2005, Application number 20060242515.

37. Grinchuk, M., A. A. Al-Yamani, and E. Chmelar, "Methods for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits," Filed with USPTO, May 18, 2005, Application number 20060282728.

Technical Presentations:

In addition to the conference presentations shown above, the following is a list of some technical presentation with their events:

1. Al-Yamani, A. "Adaptive ABFT for Matrix Multiplication," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, July 31, 2000.

2. Al-Yamani, A. "Application Level Adaptive Availability: A Case Study (Matrix Multiplication)," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, November 27, 2000.

3. Al-Yamani, A. "Remote Exploration and Experimentation (REE): Project Overview," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, November 29, 2000.

4. Al-Yamani, A. "Detection/Recomputing vs. Correction in DSP Applications," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, February 12, 2001.

5. Al-Yamani, A. "Algorithm Based Fault Tolerance: A Performance Perspective Based on Error Rate," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, April 30, 2001.

6. Al-Yamani, A. "Checksum-Based ABFT: A Performance Perspective Based on Error Rate," NASA JPL Meeting, Pasadena, CA, May 28, 2001.

7. Al-Yamani, A. "Contention and Floating Values in BIST Generation," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, August 13, 2001.

8. Al-Yamani, A. "Testing Digital Circuits with Illegal States," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, November 19, 2001.

9. Al-Yamani, A. "Low Overhead Built-In BIST Reseeding," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, March 11, 2002.

10. Al-Yamani, A. "Low Overhead Built-In BIST Reseeding," Invited Presentation at SynTest Inc., San Jose, CA, June 6, 2002.

11. Al-Yamani, A. "Testing Digital Circuits with Illegal States," Invited Presentation at SynTest Inc., San Jose, CA, June 6, 2002.

12. Al-Yamani, A. "Logic BIST: Theory, Problems and Solutions," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, August 5, 2002.

13. Al-Yamani, A. "Finding a Minimal Set of Seeds for BIST Reseeding," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, October 28, 2002.

14. Al-Yamani, A. "Seed Encoding for Linear Pseudo Random Pattern Generators," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, February 24, 2003.

15. Al-Yamani, A. "Built-In Reseeding," 12th Pacific Northwest Test Workshop (BAST’03), Bodega Bay, CA, February 26, 2003.

16. Al-Yamani, A. "ATPG and BIST: Establishing a Link," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, July 21, 2003.

17. Al-Yamani, A. "Test Set Reduction Techniques with Results from ELF35 and Murphy," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, November 10, 2003.

18. Al-Yamani, A. "ATPG and BIST: Establishing a Link," Invited Presentation at Advantest Inc., Santa Clara, CA, January 29, 2004.

19. Al-Yamani, A. "Tester Data on Pseudorandom and Deterministic BIST," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, February 9, 2004.

20. Al-Yamani, A. "Defect Levels of Pseudorandom Testing," 13th Pacific Northwest Test Workshop (BAST’04), Bodega Bay, CA, February 27, 2004.

21. Al-Yamani, A. "Defect Level Data for ELF35 Test Sets," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, May 10, 2004.

22. Al-Yamani, A. "ELF35 Test Results: Speed, Voltage and Elementary Gates," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, October 4, 2004.

23. Al-Yamani, A. "Segmented Addressable Scan Architecture," 14th Pacific Northwest Test Workshop (BAST’05), Bodega Bay, CA, February 23, 2005.

24. Al-Yamani, A. "What DPM do we need? Can we get it and how?," A panel in the 14th Pacific Northwest Test Workshop (BAST’05), Bodega Bay, CA, February 24, 2005.

25. Al-Yamani, A. "Systematic Scan Reconfiguration," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, June 13, 2005.

26. Al-Yamani, A. "Digital IC Testing Tutorial," Department of Computer Science, University of Bristol, Bristol, UK, June 28, 2006.

27. Al-Yamani, A. "Logic Analysis and Synthesis: A Tutorial," Department of Computer Science, University of Bristol, Bristol, UK, July 12, 2006.

28. Al-Yamani, A. "Energy-Delay Efficient Test," Reliability and Testing Seminar (RATS), Center for Reliable Computing, Stanford University, Stanford, CA, July 24, 2006.

29. Al-Yamani, A. "Systematic Scan Reconfiguration," Invited Presentation at the School of Electronics and Computer Science, Southampton University, Southampton, UK, July 30, 2006.

Refereeing:

A referee for the following conferences and journals:

· IEEE Transactions on Computer Aided Design

· IEEE Transactions on Computers

· ACM Transactions on Design Automation of Electronic Systems

· Springer Journal of Electronic Testing Theory and Applications

· Springer International Journal of Parallel Programming

· Elsevier Journal of Systems and Software

· The Arabian Journal for Science and Engineering

· IEEE International Test Conference

· IEEE VLSI Test Symposium

· IEEE Design Automation Conference

· IEEE International Design and Test Conference