Research

Ahmad is Involved in research in VLSI design and test, design-for-testability, built-in self-test, computer-aided design automation,  iterative heuristics and their parallelization for VLSI design,  and reliable computing. Publications below reflect the extent of involvement in each area.

MS theses committees:

1. Mustafa Imran, “Test Data Volume Reduction of Scan-Based Deterministic Test based on Scan Chains Compatibility using Partitioning & Relaxation,” M.Sc. Thesis, King Fahd University of Petroleum and Minerals, 2007 (Member).

2. Ali Zaidi, “An efficient reconfigurable archetecture for secret and public key cryptography,” M.Sc. Thesis, King Fahd University of Petroleum and Minerals, 2007 (Member).

Funded Projects:

1. Scan Test Cost and Power Reduction through Systematic Scan Reconfiguration,” KFUPM funded project, 2006-2007 (Primary Investigator).

2. Test Data Volume Reduction of Scan-Based Deterministic Test based on Scan Chains Compatibility using Partitioning & Relaxation,” Sabic funded project, 2006-2007 (Co-Investigator).

3. Energy-Delay Efficient Test,” BAE, British Council, and KFUPM funded project, 2006 (Primary Investigator).

Publications:

THESES:

1. Ahmad Al-Yamani, “A Parallel Tabu Search Algorithm for VLSI Standard Cell Placement,” M.Sc. Thesis, King Fahd University of Petroleum and Minerals, June 1999.

2. Ahmad Al-Yamani, “Deterministic Built-In Self Test for Digital Circuits,” Ph.D. Thesis, Stanford University, April 2004.

JOURNALS:

3. Al-Yamani, A.A., S. Sait and H. Youssef, "Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations," Journal of Heuristics on Parallel Metaheuristics, 8(3), pp. 277-304, May 2002.

4. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Optimized Reseeding by Seed Ordering and Encoding," IEEE Transactions on Computer-Aided Design (TCAD'04), 24(2), pp. 264-271, February 2005.

5. Al-Yamani, A.A, and E.J. McCluskey, “Test Chip Experimental Results on High Level Structural Test,” ACM Transactions on Design Automation of Electronic Systems (TODAES’05), October 2005. (Invited)

6. Al-Yamani, A., N. Devta-Prasanna, E. Chmelar, M. Grinchuk, and A. Gunda, “Scan Test Cost and Power Reduction through Systematic Scan Reconfiguration,” Accepted for IEEE Transactions on Computer-Aided Design.

CONFERENCES AND SYMPOSIA:

7. S. Sait, Youssef, Barada, and A. Al-Yamani, "A Parallel Tabu Search Algorithm for VLSI Standard Cell Placement," IEEE International Symposium on Circuits and Systems (ISCAS'00), Geneva, Switzerland, May 2000.

8. Al-Yamani, A.A., N. Oh, and E.J. McCluskey, "Algorithm-Based Fault Tolerance: A Performance Perspective Based on Error Rate," Fast Abstract, IEEE International Symposium on Dependable Systems and Networks (DSN'01), Gotenberg, Sweden, July 1-4, 2001.

9. Al-Yamani, A.A., N. Oh, and E.J. McCluskey,"Performance Evaluation of Checksum-Based ABFT," 16th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), San Francisco, CA, Oct. 24-26, 2001.

10. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Techniques for Testing Digital Circuits with Constraints," 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02), Vancouver, BC, Canada, Nov. 6-8, 2002.

11. Al-Yamani, A.A., S. Sait and H. Barada, "HPTS: Heterogeneous Parallel Tabu Search for VLSI Placement," IEEE Congress on Evolutionary Computing (CEC'02), Honolulu, Hawaii, May 12-17, 2002.

12. Al-Yamani, A.A., S. Sait, H. Youssef, and H. Barada, "Parallel Tabu Search in a Heterogeneous Environment," IEEE International Parallel and Distributed Processing Symposium (IPDPS'03), Nice, France, Apr. 22-26, 2003.

13. Al-Yamani, A.A., and E.J. McCluskey, "Built-In Reseeding for Serial BIST," 21st IEEE VLSI Test Symposium (VTS'03), Napa Valley, CA, Apr. 27-May 1, 2003.

14. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "BIST Reseeding with Very Few Seeds," 21st IEEE VLSI Test Symposium (VTS'03), Napa Valley, CA, Apr. 27-May 1, 2003.

15. Al-Yamani, A.A., and E.J. McCluskey, "Seed Encoding for LFSRs and Cellular Automata," 40th ACM/IEEE Design Automation Conference (DAC'03), Anaheim, CA, June 2-6, 2003.

16. McCluskey, E.J., A. A. Al-Yamani, C.-M. Li, C.W. Tseng, E. Volkerink, F. Ferhani, E. Li, and S. Mitra,"ELF-Murphy Data on Defects and Test Sets," 22nd IEEE VLSI Test Symposium (VTS’04), Napa Valley, CA, Apr. 25-28, 2004.

17. Salama, K.N., and A.A. Al-Yamani, " Analysis of Self-Correcting Active Pixel Sensors," SPIE's 17th Annual Symposium on Electronic Imaging Science and Technology, San Jose, CA, January 2005.

18. Al-Yamani, A.A., and E.J. McCluskey, "BIST-Guided ATPG," 6th IEEE International Symposium on Quality Electronics Design (ISQED'05), San Jose, CA, March 21-23, 2005.

19. Al-Yamani, A.A., Erik Chmelar and Mikhail Grinchuk, "Segmented Addressable Scan Architecture," 23rd IEEE VLSI Test Symposium (VTS'05), Palm Springs, CA, May 1-5, 2005.

20. Park, I., A. Al-Yamani, and E.J. McCluskey, “Effective TARO Pattern Generation,” 23rd IEEE VLSI Test Symposium (VTS'05), Palm Springs, CA, May 1-5, 2005.

21. Al-Yamani, A.A., N. Devta-Prasanna, and A. Gunda, “Should Illinois-Scan Architectures be Centralized or Distributed,” IEEE International Symposium on Defect and Fault Tolerance (DFT’05), Monterey, CA, Oct 3-5, 05.

22. Al-Yamani, A “DFT for Controlled-Impedance IO Buffers,” 43rd ACM/IEEE Design Automation Conference (DAC'06), San Francisco, CA, July 24-26, 2006.

WORKSHOPS:

23. Al-Yamani, A.A., and E.J. McCluskey, "Low-Overhead Built-In BIST Reseeding," 3rd IEEE International Workshop on Test Resource Partitioning (TRP'02), Baltimore, MD, Oct. 10-11, 2002.

24. Al-Yamani, A.A., and E.J. McCluskey, "Test Quality for High Level Structural Test," IEEE High Level Design Validation and Test (HLDVT'04), Sonoma, CA, November 2004.

TECHNICAL REPORTS:

25. Al-Yamani, A.A., S. Mitra, and E.J. McCluskey, "Avoiding Illegal States in Pseudorandom Testing of Digital Circuits," Stanford CRC TR 02-02.

26. Al-Yamani, A.A., and E.J. McCluskey, "Built-In Reseeding for Built-In Self Test," Stanford CRC TR 02-03.

PATENTS:

27. Grinchuk, M., A. A. Al-Yamani, and E. Chmelar, "System And Method For Implementing Postponed Quasi-Masking Test Output Compression In Integrated Circuit," Filed with USPTO, Dec 16, 2004, Application number 20060156128.

Technical Presentations:

Presented all 1st author papers in their corresponding conferences and workshops and was invited to give several technical presentations to high-tech companies and workshops in the silicon valley, and to some universities in the US and the UK

Refereeing:

A referee for the following conferences and journals:

· IEEE Transactions on Computer Aided Design

· IEEE Transactions on Computers

· IEEE International Test Conferenc

· IEEE VLSI Test Symposium

· IEEE Design Automation Conference

· Elsevier Journal of Systems and Software

· The Arabian Journal for Science and Engineering