COE 305 
Post a new question: send E-mail to Dr. Atef Jawad Al-Najjar
|1||If two 16-bit registers are used to define the base address and offset. What is the maximum possible address bus width? Provide a possible design.||32-bits address bus.
Concatenate the two registers.
|2||The data bus is unidirectional (True/False)||False.|
|3||If the address and data lines are not time-multiplexed, which control signal becomes un-necessary?||ALE|
|4||List three solutions when memory access time does not meet processor access time requirements.||Slow CPU clock.
Buy faster memory.
Add wait states.
|5||If the instruction queue is increased to 20 bytes, and 50% of the instructions are jump instructions, then performance is expected to increase or decrease?||It depends!
Increasing the size of the instruction pipeline helps for consecutive instructions.
|6||When interfacing to a CPU, the maximum number of loads is calculated using low-state D.C. current values. (True/False), Explain.||False. Both the high-state and low-state (Logic-1 and logic-0) must be calculated.|
|7||When interfacing digital logic components, three parameters must be considered. List them.||Voltages, Currents, and Time.
|8||Given a Pentium processor. Data transfer rate in pipelined burst mode is higher than regular burst mode (True/False). Explain.||True. Burst mode takes 5 (2+1+1+1) clock states to move 32 bytes. pipelined burst mode takes only 4 (1+1+1+1) clock states.|
|9||Why was the 8088 manufactured with an 8-bit external data bus? (Hint: Memory was expensive.)||Requires only one memory bank, making it more economical!|
|10||Using tri-state buffers, how to find the leakage current? (Hint: For the high-state, all devices must be in the high-impedance state.)||Look for the I_OZ in the data sheet. Can be I_OZL or O_OZH, with typical values of 10 or 20 microApms.|
|11||When calculating the maximum and minimum values of the pull-up resistor, where does the 2.6V and the 4.6V come from?||Please study the derivation we had in class. Remember we used V_in >= V_IH for high state, and V_in <= V_IL for low state. Also remember how the values change to take noise-immunity into consideration!|
|12||What is the NDP processor?||NDP stands for numerical data processor, which is the math co-processor.|
|13||How does ALE , ~DEN and DT/~R work together? What is the relation between them?||ALE is active during T1 to demultiplex address/data signals. ~DEN is used to enable data buffers, and DT/~R is used to switch the direction of data buffers. Remember, the data-bus is bi-directional!|
|14||How does the IF flag mask the INTR input pin?||Using a two-input AND gate, with IF as one input and the INTR input pin as the second input. When IF=0, INTR is 'masked'.|
|15||In Fig. 6.8 , p 235 (Handout), what is the difference between Reset (min) and Reset(max)?||Design for the worst case. Take the min.|