Execution Control Sequence for Add Instruction 
Let us consider the instruction ADD R1, [R3] (R1← R1 + [R3]) and derive its execution control sequence.

Execution of this instruction requires the following:
1. Read the content of memory location pointed by R3
2. Perform the addition
3. Load the result into R1

The control sequence for this instruction using the single-bus CPU is shown in the next table:

Control Sequence Active Signals
T4 R3out, MARin, Read
T5 R1out, Yin, WMFC
T6 MDRout, ALU (C=A+B), Zin
T7 Z1out, R1in, END

After fetching the instruction, the next clock transfers the control to T4 which is the start of the execution control sequence for this instruction. In T4, the content of R3 is put on the CPU bus by activating the signal R3out and this value is captured in MAR and the Read signal is activated. In this cycle, a memory read operation is performed reading the content of the address stored in R3. In T5, while waiting for the memory to finish the requested read operation, the content of R1 is stored in the Y register. The signal WMFC will ensure that the CPU will remain in T5 and not go to T6 until the memory finishes the requested operation. Once the requested read operation is complete, the MDR will contain the read operand and CPU will go to T6. In T6, the content of MDR (which contains the read operand) is put on the CPU bus and an ALU addition operation is selected. This will add the content of Y (which is the stored content of R1) and the read operand, and store the result in the Z register. In T7, the content of Z register is put on the CPU bus and is captured in R1. Note that the END signal is also activated to indicate the end of the execution control sequence for this instruction. This signal will cause the CPU go to T1 in the next clock cycle for fetching the next instruction.

The execution control sequence of the ADD R1, [R3] instruction for the single-bus CPU is demonstrated in the next figure:

Fig. m300124.1 Execution Control Sequence for ADD Instruction in a Single-Bus CPU