As we have seen, information is processed in the data path by register transfers. In a register transfer operation, information is moved out of a register, along a bus, possibly through combinational logic, and into another register. These actions take time, and in this section we will discuss how much time they take Being able to estimate the timing of such actions is crucial in determining the maximum clock frequency that a circuit will support.

The next figure shows an example of the clocking and timing relationships that exist along the data path. The figure shows the information being propagated from register R1, the transmitter, through tri-state buffer and bus, through a combinational logic block such as an ALU into register R2, the receiver. Propagation time through the wires interconnecting the registers and logic gates is assumed negligible in this example.

Fig. m300116.1 Register Transfer Timing

The figure follows the signal as it travels from output register to input register:

	1. The information propagates through the tri-state buffer in tg time.
	2. The information then travels across the bus in time tbp.
	3. The information propagates through the ALU or other combinational logic block in time tcomb.
	4. The signal arrives at R2. The data has to arrive at the input of R2 and be stable before the capture clock of R2 by the flip-flop setup time tsu. After the capture clock of R2 is activated, the data will be stored in R2 after a flip-flop propagation delay tff.

Estimating the Pulse Width

In order for the value of R1 to be captured correctly at R2, the width of the clock pulse has to satisfy the following relation:

t_w >= t_g + t_bp + t_comb + t_su

Estimating the Minimum Clock Period

The minimum clock period for a register transfer is the time required to propagate data entirely around the circuit, so that the new value is in the destination register and ready for another cycle. The minimum clock period for this particular register transfer is

t_clk= t_g + t_bp + t_comb + t_su + t_ff

Note that there is no concern about the hold time since the pulse width will always be greater than t_h.

Example Timing Parameters

Example timing parameters for National Semiconductor FAST TTL gates and flip-flops and VITESSE GaAs gate-array components are shown in the following table.

Name	Parameter	FAST Delays	VITESSE Delays
Tri-state buffer propagation time	tg	5 ns	150 ps
Bus propagation time (assumed)	tbp	5 ns	500 ps
Logic delay	tcomb	14 ns	400 ps
Flip-flop propagation time	tff	6 ns	440 ps
Flip-flop setup time	tsu	2 ns	146 ps
Flip-flop hold time	th	3 ns	104 ps

The table contains only the pessimistic values: the maximum propagation delays and setup and hold times. The prudent engineer will add a 10% "Murphy's law factor" to these values to account for variation in test equipment and power supply voltage, and the possibility that some parts from the vendor will be outside the specification range.

Example: Calculate the maximum clock frequency for the circuit structure given in the first figure using the data from the above table.

For the FAST TTL parts, the minimum clock period is given by

tmin = tg + tbp + tcomb + tsu + tff = 5 + 5 + 14 + 2 + 6 = 32 ns

We add 10% safety margin, tmin = 35.2 ns.

Therefore, the maximum clock frequency = 1/(35.2 ns) = 28.4 MHZ.

For the VITESSE gate array, the minimum clock period is given by

tmin = tg + tbp + tcomb + tsu + tff = 150 + 500 + 400 + 146 + 440 = 1636 ps

We add 10% safety margin, tmin = 1799.6 ps.

Therefore, the maximum clock frequency = 1/(1799.6 ps) = 555.7 MHZ.