Introduction
Register Transfer
Data Path Design
Register Transfer
Register Transfer Timing
Single-Bus CPU Design
Fetch Control Sequence
Synchronous vs. Asynchronous Memory Transfer
Execution Control Sequence for Add Instruction
Execution Control Sequence for JMP Instruction
Execution Control Sequence for Conditional JMP Instruction
Execution Control Sequence for Additional Instruction
Performance Considerations
Two-Bus CPU Design
Execution Control Sequence for Add Instruction
Execution Control Sequence for Unconditional and Conditional Jump Instructions
Three-Bus CPU Design
Execution Control Sequence for Add Instruction
Execution Control Sequence for Unconditional and Conditional Jump Instructions
