So far, when we generated the execution control sequence for an instruction we were assuming the knowledge of the particular operands and derived the execution control sequence accordingly. However, a designer when writing the execution control sequence for an instruction does not know what are the operands until the instruction is fetched. So, the execution control sequence for an instruction has to be written in a general way regardless of the actual operands. Let us clarify this by an example.

Let us consider the instruction ADD R0, R1 (R0← R0 + R1) on the single-bus CPU. The execution control sequence for this instruction is given below:

T4 R1out, Yin
T5 R0out, ALU (C=A+B), Zin
T6 Zout, R0in, END

The designer needs to write this execution control sequence in general such that the source and destination operands can be any register. Then, the particular Rout and Rin signals will be derived by the control unit after the instruction is fetched and the operands are known. The general execution control sequence for this instruction can be written as:

T4 Rsrc,out, Yin
T5 Rdst,out, ALU (C=A+B), Zin
T6 Zout, Rdst,in, END

So, here the control unit will generate three general signals Rsrc,out, Rdst,out, and Rdst,in. The derivation of the particular register signals after the instruction is fetched is illustrated below.

Fig. m300145.1 Deriving Register Control Signals

In this circuit, it is assumed that the CPU has 4 registers. So, there are 2 bits for the source operand and 2 bits for the destination operand. A 2x4 decoder is used to decode the source operand and generate a signal for each register (R0, R1, R2, and R3). So, if the source operand is R0, the R0 signal will be 1 and all the other signals will be 0. If it is R1, then the R1 signal will be 1 and so on. Similarly, a 2x4 decoder is used to decode the destination operand and generate a signal for each register (R0, R1, R2, and R3). So, if the destination operand is R0, the R0 signal will be 1 and all the other signals will be 0. If it is R1, then the R1 signal will be 1 and so on.

Let us assume that the fetched instruction is ADD R0, R1. In this case, the output of the source decoder will make R1 1, call it R1,src, and the output of the destination decoder will make R0 1, call it R0,dest. Then, in T4 when Rsrc,out is 1, R1out becomes 1 since R1src is 1. In T5, when Rdst,out is 1, R0out will be 1 since R0,dst is 1. In T6, when Rdst,in is 1, R0in will be 1 since R0,dst is 1. Thus, the particular register signals are derived correctly.