In addition to specifying the operation to be performed, instructions should also specify the locations of operands and results and the location of the next address if it is different from the default location stored in the IP

Machines are classified based on operand and result locations into three main categories: Load-Store Machines: These are also known as register-to-register or general register machines Memory access is restricted to load and store instructions only. A load instruction moves data from memory to a CPU register and the store instruction moves data from CPU to memory Load and store instructions have two operands; one in a register and another in memory. The register address is considered ½ an address since it requires less bits. Hence these machines are also classified as 1½-Address machines Fig. m300230.1 Below illustrates a genral register (i.e. a 1½-Address) load-store machine and its instruction formats. An example of ADD operation is shown. Operands have to be loaded into CPU register before they can be added. Fig. m300230.1 A 1 1/2-Address Load-Store Machine and its instruction formats The reduction in the address fields reduces the size of machine instructions and simplifies the CPU design Operands and results of ALU and branch instructions only reside in CPU registers. This makes these instructions very efficient These machines however, are very inefficient for data-intensive applications (like multi-media) where large volume of data need to be processed and hence be moved in and out of the CPU Most RISC machines are of this type Register-Memory Machines: These machines locate operands and result in a combination of memory and registers One of the operand or the result must be an accumulator or general register, thus these machines are 1- or 1½-Address machines Fig. m300230.2 illustrates a 1-Address machine and its instruction format. An accumulator holds one of the operands and the result while the other operand is located in the memory. Fig. m300230.2 A 1-Address Machine and its instruction formats The accumulator can be loaded from memory or its content stored to memory, reducing the instruction size significantly Again 1-Address machines are very inefficient with data-intensive applications Memory-Memory Machines: These machines allow both the operands and the result to reside in memory They are classed as 2- or 3-address machines. In 2-address machines one of the operands also serves as the result location Fig. m300230.3 illustrates a 3-Address machine with 24-bit-wide address bus and its instruction format. The instruction length is very large because of the three memory addresses A 2-Address machine and its instruction format is illustrated in Fig. m300230.4 . The compromise of storing the result in one of the operands location reduces the instruction length significantly Fig. m300230.3 A 3-Address Machine and its instruction formats Fig. m300230.4 A 2-Address Machine and its instruction formats Many machines combine instructions from different classes (i.e. 1-Address, 1½-Address, 2-Address, and 3-Address formats) trading off number of instructions per program for number of bits per instruction Variable length instructions are widely used to optimize the performance across different instruction classes