The execution control sequence for the JMP Label instruction for the two-bus CPU is given in the following table:

Control Sequence	Active Signals
T4	PCout, ALU (C=B), Yin
T5	(offset-field-of-IR)out, ALU (C=A+B), PCin, END

As can be seen, the number of execution control sequences for the JMP instruction is two for the two-bus CPU design while it is three in the single-bus CPU. So, there is a saving of one clock cycle in the execution of the instruction.

The execution control sequence of the JMP Label instruction for the single-bus CPU is demonstrated in the next figure:

Fig. m300134.1 Execution Control Sequence for JMP Instruction in a Two-Bus CPU

The execution control sequence for the JMPN Label instruction for the two-bus CPU is given in the following table:

Control Sequence	Active Signals
T4	PCout, ALU (C=B), Yin, If (N=0) then END
T5	(offset-field-of-IR)out, ALU (C=A+B), PCin, END

Similarly, there is a saving of one clock cycle in the execution control sequence for the JMPN instruction in the two-bus CPU compared to the single-bus CPU.