Register Transfer 

The process of instruction execution or any function performed inside the CPU can be described as a set of register transfer operations. In each clock, one or more register transfer operations are performed. The following table shows a set of 8086 instructions and their corresponding register transfer operations:

Instruction Register Transfer
INC AX AX ← AX + 1
JMP Label PC ← Label

Due to the given CPU design, some of these register transfer operations can not be implemented in one clock cycle and have to be broken into a number of register transfer operations that have to be performed in a sequence. For example, consider the implementation of instruction ADD AX, BX in a single-bus CPU design. It is not possible to execute this instruction in a single register transfer operation because there is a single bus connected to the ALU and we cannot put both operands AX and BX on the bus in the same time. Also, the result cannot be put back from the ALU to the bus in the same cycle. In this case, the instruction will be executed in three register transfer operations based on the single-bus CPU given in the introduction, as shown below:

Example: Register Transfer Sequence for Executing the Instruction ADD AX, BX.
 1. Y ← AX
 2. Z ← Y + BX
 3. AX ← Z

We next relate data transfer operations to the logic circuits that implement them. It is important to consider not only where the data moves but when. If A and B are m-bit registers, the register transfer A ← B can be implemented by two sets of m flip-flops as shown below.

Fig. m300114.1 Multiple-Bit Register Transfer

The m-bit data is moved (copied) from register B into register A when the strobe signal is activated. Assuming rising-edge triggered flip-flops, the transfer operation occurs on the rising edge of the strobe

In order to transfer data between n registers, this can be achieved by interconnecting the registers using n multiplexers such that the input of each register is connected to an (n-1)x1 multiplexer. In the (n-1)x1 multiplexer, the other n-1 registers are connected to the n-1 inputs of the multiplexer and log (n-1) selection lines are used to select the required register. This solution is expensive as it requires complex routing of the wires between the n registers in addition to the n multiplexers and n log (n-1) selection lines. The next figure shows three single-bit registers interconnected using multiplexers. Note that in this structure, each register is connected to the other two registers using a 2x1 MUX. Also, the capture of the value for each register is controlled by a control signal.

Fig. m300114.2 Register Transfer with Multiplexers

Instead, a better solution is to use a tri-state bus that is shared among all registers. In this case, all the registers are connected to the bus through tri-state buffers such that one tri-state buffer is enabled at a time. Each tri-state buffer is controlled by an output enable signal that when set high connects the input of the buffer to the output otherwise produces a high-impedance value Z. The next figure illustrates the operation of a tri-state buffer.

Fig. m300114.3 Tri-State Buffer

The bus will be connected to the input of all registers. This structure allows any register to transfer its value on the bus which will reach all the registers interconnected by the bus. In order to control, which register will capture the value on the bus, we need a strobe signal for each register. To allow for propagation delay across the bus and for FF setup time, the registers capture on the falling edge of the clock while the tri-state buffer enable signals are assumed to be activated on the rising edge of the clock. This is achieved by Anding the strobe signals with the complement of the clock. The next figure shows two registers interconnected using the tri-state bus structure.

Fig. m300114.4 Basic Register Transfer Control Signals

To transfer the content of register R1 to register R2, the R1out signal and R2in signal are enabled on the rising edge of the clock. This puts the value of R1 on the bus and makes R2 capture the bus value on the falling edge of the clock.

The next figure shows three single-bit registers interconnected using the tri-state bus structure.

Fig. m300114.5 Registers Interconnected by a Tri-State Bus