Computer Organization
Introduction
CPU Design
Introduction
Data Path Design
Register Transfer
Register Transfer Timing
Single-Bus CPU Design
Fetch Control Sequence
Synchronous vs. Asynchronous Memory Transfer
Execution Control Sequence for Add Instruction
Execution Control Sequence for JMP Instruction
Execution Control Sequence for Conditional JMP Instruction
Execution Control Sequence for Additional Instruction
Performance Considerations
Two-Bus CPU Design
Execution Control Sequence for Add Instruction
Execution Control Sequence for Unconditional and Conditional Jump Instructions
Three-Bus CPU Design
Execution Control Sequence for Add Instruction
Execution Control Sequence for Unconditional and Conditional Jump Instructions
Control Unit Design
Introduction
Hardwired Control Unit Design
Generation of Control Signals
Deriving Rout & Rin Signals for Registers
CPU-Memory Interface Circuit
Microprogrammed Control Unit Design
Microprogrammed Control Unit Operation
General Microprogrammed Control Unit Organization
Microinstruction Formats
Microprogram Example for Add Instruction with Addressing Modes
Hardwired vs. Microprogrammed Control Unit
Simple CPU Design Example
