We have seen before that the CPU-Memory interface includes the data bus, address bus and some control signals including Read, Write, and Memory-Function-Complete (MFC). The CPU is interfaced to the data bus and address bus through the MDR and MAR registers, respectively.
In addition to this interface, there is a need for a CPU-Memory interface circuitry to manage their interaction. When the CPU wants to perform a read or write operation, it asserts either the Read or Write signal and puts the address to be read from or written to in the MAR register. Then, the CPU waits for the memory to finish the requested transfer operation. It is required that the CPU keeps the Read or Write signal set until the memory finishes the requested operation. The memory activates the MFC signal when the requested operation is completed. One the MFC is set to 1, and then the Read or Write signal can be set to 0. This interaction process between the CPU and memory is called handshaking.
A versatile CPU can communicate with main memory modules of different speeds
The CPU-memory interface circuit should handle both fast and slow memories. Recall that internal signals generated by the control unit are active for one clock cycle during a given control step. Slow memory has to see those signals for more than one clock cycle. So, the CPU-memory interface circuit has to keep the Read or Write signals set to 1 until the MFC signal becomes 1. This is because the CPU will set them to 1 for one clock cycle and then go to the next control step when they may become 0.
It is assumed here that the memory is falling-edge triggered i.e., MFC signal will change value on the falling-edge of the clock. However, the control unit is rising-edge triggered and changes values of control signals on the rising edge of the clock.
The CPU-Memory interface circuit is shown below.
Note that the Read signal is connect to a 2-input AND gate, a JK-flip-flop, and a 2-input OR gate. This circuitry is designed to keep the Read signal 1 when set until the MFC is set to 1. Once the MFC signal becomes 1 on the falling-edge of the clock, the Read signal goes to 0 on the next rising-edge of the clock. This circuitry is connected to a D-flip-flop that is triggered on the falling-edge of the clock. The purpose of this D-FF is to make the Read signal becomes negative-edge triggered. Note that MAR loads the value on the negative-edge of the clock. Thus, this way, the Read signal will be seen by the memory set to 1 when the address contains the address to be read from memory.
Initially it is assumed that the MFC signal is 0. Assume that the Read signal is set to 1. This will make the 2-input AND gate become 1 and also 2-input OR gate (R) 1. Also, note that the J input of the JK-FF becomes 1 while the K input is 0 since it is connected to MFC. On the next rising-edge of the clock, assume that the Read signal will become 0 as the control unit goes to the next control step. At this point, the output of the 2-input AND gate will go to 0. However, the output of the JK-FF will become 1 sine the JK inputs where 1 and 0 at the rising-edge of the clock which sets the JK-FF to 1. Thus, the output of the 2-input OR gate (R) remains 1. Thus, the R signal and the MR signal keep their value which is what is required.
Next, assume that on the next falling-edge of the clock the MFC signal becomes 1. This makes the J input of the JK-FF 0 and the K input 1. Thus, on the next rising-edge of the clock, the JK-FF will reset to 0 and the R signal becomes 0. Thus, the handshaking process is achieved.
A similar circuit is implemented for the Write signal to achieve the same functionality. An additional functionality of the CPU-Memory interface signal is to make the control unit remain in the same control step when a Read or Write operation were requested and the memory did not finish its function (i.e. MFC did not become 1) and the WMFC signal is 1. This is achieved by adding a 2-input OR gate that Ores the R and W signal to indicate that a Read or Write signal is requested. This is connected to a 3-input Nand gate generating the RUN signal. The RUN signal is ANDED with the clock and controls the clock of the step counter. So, if RUN is 0 the step counter is not clocked and will remain in the same control step. Note that RUN becomes 0 if there is a Read or Write operation and the memory did not finish its operation (MFC=0) and the WMFC=1. When MFC becomes 1 on the falling-edge of the clock, RUN becomes 1, so on the next rising-edge of the clock the control step counter increments and goes to the next control step.
Next, let us consider the following sequence of control steps:
T1 Read, WMFC T2 Write T3 WMFC T4 ....
The timing diagram corresponding to this control sequence is shown below:
A Read request is initiated in T1 and due to the WMFC signal in T1 the step counter will remain in T1 in the next clock cycle since MFC is 0. Since MFC becomes 1 in the second clock cycle, the Run signal becomes 1 so the step counter goes to T2 in the third clock cycle. Note that because MFC becomes 0 in the falling edge of the third clock (T2) a Read or Write request in T2 will not be seen in T2 since T1 has a WMFC signal. As can be seen from the timing diagram, while the Write request is initiated in T2, the MW signal becomes 1 in T3. So, in general a Read or Write request will not be seen in a cycle following a cycle that has a WMFC signal. The request is delayed by one clock cycle.
Note that WMFC signal can be put in the same cycle with a Read or Write signal. Also, note that WMFC signal can not be in the same cycle with END signal. This is because the next cycle, T1, has a Read signal.