Having three buses in a CPU design means that all three buses can be used in ALU operations, two for the source operands and one for the result. The next figure shows a three-bus CPU design with three buses A, B, and C corresponding to the ALU inputs and outputs.

Fig. m300136.1 Three Bus CPU

So, in this design no temporary registers are needed to be connected to the ALU to temporarily hold an operand or the result. In this design, an ALU operation can be performed in one cycle, unlike the single-bus and two-bus CPU designs. This is both operands can be put on the A bus and B bus simultaneously and the result put on the C bus.

Note that in this design, each of the registers R1-R4 is connected to bus A and bus B. So, each of these registers can place a value on either of the buses. Thus, each register has two OUT control signals one for the A bus and the other for the B bus. For example, R1out,_A controls the tri-state buffer connecting R1 to the A bus, while R1out,_B controls the tri-state buffer connecting R1 to the B bus.

Note that IR is connected only to the A bus, while PC and MDR are connected only to the B bus. Note also that the input of all registers is connected to the C bus. However, the input of the MAR register is also connected to the B bus. So, there are two control signals for loading a value to MAR namely, MARin,_C and MARin,_B. The input of MAR will be connected to a multiplexer to select the input either from the B or C bus. p> The fetch control sequence of the three-bus CPU design is illustrated next. In order to fetch an instruction from memory in the three-bus CPU, this requires two control steps and at least two clock cycles as shown below:

Control Sequence	Active Signals
T1	PCout, MARin,B, Read, ALU (C=B+1), PCin, WMFC
T2	MDRout, ALU (C=B), IRin

Note that the number of clock cycles required to fetch an instruction in the three-bus CPU design is less than both two-bus and single-bus designs by one clock cycle. The fetch control sequence for the three-bus CPU design is illustrated next.

Fig. m300136.2 Fetch Control Sequence for Three-Bus CPU