Execution Control Sequence for Add Instruction 
Let us consider the instruction ADD R1, [R3] (R1← R1 + [R3]) and derive its execution control sequence for the two-bus CPU design. The control sequence for this instruction using the two-bus CPU is shown in the next table:

Control Sequence Active Signals
T4 R3out, ALU (C=B), MARin, Read
T5 R1out, ALU (C=B), Yin, WMFC
T6 MDRout, ALU (C=A+B), R1in, END

The execution control sequence of the ADD instruction for the two-bus CPU is demonstrated in the next figure:

Fig. m300133.1 Execution Control Sequence for ADD Instruction in a Two-Bus CPU

The number of clock cycles for the ADD instruction is 6 in the two-bus CPU, including the fetch clock cycles, while it is 7 in the single-bus CPU. Thus, there is a speedup gain in the number of clock cycles required to execute the add instruction by one clock cycle.

The percentage speedup can be computed as follows:

%Speedup = (f2-bus - f1-bus)/f1-bus      x 100=(1/T2-bus - 1/T1-bus)/1/T1-bus      x 100= (T1-bus - T2-bus)/T2-bus      x 100

As an example for computing speedup, let us assume the following:
1. Instruction count is the same in both single-bus and two-bus CPU designs.
2. All instructions execute in the two-bus CPU in 7 cycles instead of 8 in the single-bus CPU.
3. Clock period is the same for both designs.

%Speedup = (IC x 8 x τ - IC x 7 x τ)/IC x 7 x τ    x 100
         = 14%

However, if we look more carefully at the organization of the two-bus CPU design we will notice that it requires two-bus propagation delays instead of one. This implies that the clock period on the two-bus design will be larger than that in the single-bus CPU design. Assume 10% increase in the clock period.

%Speedup = (IC x 8 x τ1 - IC x 7 x 1.1 τ1)/IC x 7x 1.1 τ1    x 100
         = 3.9%

Thus, the performance advantage gained by decreasing CPI may be lost due to increase in clock period.