Two-Bus CPU Design 

In the next figure, a two-bus CPU design is shown. In this design, information travels out of the registers on the B bus, labeled "Out Bus", and into the registers on the A, or "In Bus". Note that in this design, the C register connected to the output of the ALU is eliminated as the ALU output can occupy the A bus while one of the operands is on the B bus.

Fig. m300132.1 Two Bus CPU

In order to perform a register transfer operation in this design, the value must be gated onto the Out bus, and strobed in from the In bus. There is only one way to interconnect the B bus with the A bus, and that is through the ALU. The ALU function C=B copies the contents of the B bus to the C output of the ALU, and from there to the A bus.

The fetch control sequence of the two-bus CPU design is illustrated next. In order to fetch an instruction from memory in the two-bus CPU, this requires three control steps and at least three clock cycles as shown below:

Control Sequence Active Signals
T1 PCout,ALU (C=B), MARin, Read
T2 PCout, ALU (C=B+1), PCin, WMFC
T3 MDRout, ALU (C=B), IRin

Note that the number of clock cycles required to fetch an instruction in the two-bus CPU design is the same as the single-bus CPU design. So, no reduction in the number of cycles needed for the fetch phase between the two designs.

Fig. m300132.2 Fetch Control Sequence for Two-Bus CPU