Execution Control Sequence for Additional Instruction 

In this section, we will consider several examples where we generate the execution control sequence for a number of instructions for the single-bus CPU.

Example: Generate the execution control sequence for the instruction ADD R1, 2 (R1← R1 + 2) for the single-bus CPU.
          T4 R1out, Yin
          T5 (constant-field-of-IR)out, ALU (C=A+B), Zin 
          T6 Zout, R1in, END
 

Example: Generate the execution control sequence for the instruction XCHG R1, R2 (R1← R2; R2← R1) for the single-bus CPU.
          T4 R1out, ALU (C=B), Zin
          T5 R2out, R1in
          T6 Zout, R2in, END
 

Note that in this example the Z register is used as a temporary register to perform the exchange operation. However, none of the program accessible registers can be used for this purpose (e.g. R1, R2, R3, R4).

Example: Generate the execution control sequence for the instruction INC [R1] ([R1]← [R1]+1) for the single-bus CPU.
          T4 R1out, MARin, Read, WMFC
          T5 MDRout, ALU (C=B+1), Zin
          T6 Zout, MDRin, Write, WMFC
          T7 END
 

In this example, we first read the operand to be incremented from memory. Then, we increment the operand and store it back. Note that MAR is loaded with the address of the operand in T4 and will remain having that address in T4-T7. The reason why the END signal is not placed in T6 in this example will be illustrated later when describing the CPU-Memory interface circuitry.

Example: Generate the execution control sequence for the instruction CMP R1, R2 (R1-R2) for the single-bus CPU.
          T4 R1out, Yin
          T5 R2out, ALU (C=A-B), FLAGSin, END
 

The CMP instruction subtracts the second operand from the first, and based on the result updates the flags. So, it is assumed here that there will be a FLAGS register that will store the flags and there will be a unit to compute the flags. The FLAGSin signal will control loading the values into the FLAGS register.

Example: Generate the execution control sequence for the instruction LOOP Next for the single-bus CPU.
          T4 R1out, ALU (C=B-1), Zin
          T5 Zout, R1in, If (Z=0) then END
          T6 PCout, Yin
          T7 (offset-field-of-IR)out, ALU (C=A+B), Zin
          T8 Zout, PCin, END
 

In this example, it is assumed that the loop counter is stored in register R1. So, R1 is decremented first and in T5 if the Z register contains 0 which is the result of decrementing R1, then the END signal will be activated to indicate the end of the execution of the instruction and that the loop instruction will terminate. Otherwise, a similar action to the JMP instruction is performed.