Execution Control Sequence for Conditional JMP Instruction 
Unlike unconditional Jump instruction, conditional jump instructions perform the jump if a condition is satisfied. Let us consider the branch on Negative instruction JMPN Label (PC← Label if N=1) and derive its execution control sequence. Here we assume the sign flag is N. So, if the sign flag is 1, indicating that the answer is negative, the branch is taken and the PC is loaded with the address of Label.

The execution control sequence for the JMPN Label instruction for the single-bus CPU is given in the following table:

Control Sequence Active Signals
T4 PCout, Yin, If (N=0) then END
T5 (offset-field-of-IR)out, ALU (C=A+B), Zin
T6 Zout, PCin, END

In T4, the content of PC is stored in the Y register. If the sign flag N=0, then the END signal will be activated in this cycle making the next control sequence generated T1 instead of T5. This means that the branch is not taken and the execution of the instruction is finished in one clock cycle. Note that the content of the PC stored in the Y register will not be used. In this case, the next instruction to be fetched will be the one following the JMPN instruction. If N = 1, it means that the branch will be taken and the END signal will not be activated. In this case, the next control sequence will be T5. The activation of the END signal is conditional based on the sign flag N. In T5, the offset field of the IR, which contains Label-PC, is put on the CPU bus and added with Y and the result is stored in Z. At this point Z will contain the actual address of Label. In T6, the content of the Z register, which is the address of Label, is stored in PC and the execution control sequence is terminated by the END signal.

The execution control sequence of the JMPN Label instruction for the single-bus CPU is demonstrated in the next figure:

Fig. m300128.1 Execution Control Sequence for JMPN Instruction in a Single-Bus CPU