Data transfer between the CPU and memory can be either synchronous or asynchronous. In the synchronous transfer, it i sassumed that a memory transfer operation (i.e. read or write) can be completed in a fixed and predetermined number of clock cycles. In this case, whenever the CPU requests a memory operation, it will wait for the required number of cycles and after that it knows that the operation has been completed. The synchronous transfer leads to simpler implementation, but can't accommodate devices of widely varying speeds.

In the asynchronus transfer, the CPU after requesting a memory operation wailts until the memory indicates that it completed the requested operation by setting a memory function complete signal to 1. The CPU-Memory interface is shown below.

Fig. m300122.1 CPU-Memory Interface

In the asynchronous transfer, the CPU puts the address in MAR and issues a read/write signal. The CPU then waits the memory function complete signal to be set to 1. It is assumed that the read/write signals will remain set until the memory function complete signal is set to 1. Once the memory function complete signal is set to 1, the read/write signals are cleared and the data on the data bus is loaded into MDR and can be used by the CPU.

The next table shows the fetch control sequence for both the asynchronous and synchronous memory transfer. It is assumed the memory read operation will take two clock cycles to comlete. Unless specified, we will assume asynchronous memory transfer.

Asynchronous Transfer	Synchronous Transfer
T1 PCout, MARin, Read, ALU (C=B+1), Zin	T1 PCout, MARin, Read, ALU (C=B+1), Zin
T2 Zout, PCin, WMFC	T2 Zout, PCin
T3 MDRout, IRin	T3
	T4 MDRout, IRin