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Computer Organization & Assembly Programming
HW# 1
Due date: Wednesday, Sep. 22
What is the ISA (instruction set architecture) of a computer?
Briefly describe the main functionality of the program counter register (PC), the instruction register (IR), and the fetch-execute process in a computer.
Describe two advantages for programming in assembly and two advantages for programming in a high-level language.
Represent the following numbers in binary, octal, and hexadecimal. Use as many bits as needed, and approximate the fraction upto 5 digits:
123.22
555.75
Express the following numbers in both sign-magnitude and 2`s complement notations, assuming 16-bit representation:
1111
321
Perform the following operations twice, once for a sign-magnitude notation and once for 2`s complement notation. Indicate in your answer when an overflow occurs:
010101 + 001011
110111 - 111001
A microcontroller uses 8-bit registers. Give the following in both binary and decimal:
The maximum unsigned number that can be stored.
The smallest (negative) number and the largest (positive) number that can be stored using the sign-magnitude notation.
The smallest (negative) number and the largest (positive) number that can be stored using the 2`s complement notation.
If you type the phrase COE-205 on your keyboard, what is the binary sequence sent to the computer using 8-bit ASCII with the 8th bit being an even parity bit.
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Problem 4.8.Problem 4.10.Problem 4.12.
Problem 4.16.Problem 4.17.
Given a manufacturing process with a certain yield Y and a test with certain fault coverage. Plot the Defect level (DL) curve as a function of the fault coverage for the cases when the yield Y=0.2, 0.4, 0.6 and 0.8 based on the following:
Formula derived in class.
The Williams and Brown model: DL=(1-Y)(1-d) , where d is the defect coverage of the test. Assume that d is equal to the fault coverage as an approximation. Compare the defect level curves in (i) and (ii).Consider an n-input XOR gate:Determine the minimum number of SSFs faults that has to be targeted to detect all the SSFs in the gate.Determine the minimum number of test vectors required to detect all the SSFs.Let Z(x) be the function of a single-output Combinational circuit N.
Give an example of a single stuck-at fault that changes the function from Z(x) to Z(x)`.
Show that if N is an irredundant circuit, then none of the SSFs in N can change its function from Z(x) to Z(x)`.
Consider the circuit shown in Figure 4.23:Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence relation. Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence and dominance relations. Starting with the set of faults based on the checkpoint theorem (Theorem 4.2), perform fault collapsing using the equivalence and dominance relations. Compare the set of collapsed faults to what you obtained in (ii).
Perform fault collapsing using HITEC. Compare the collapsed fault set to what you obtained in (ii) & (iii).
Consider the 2-bit counter shown below, where Q0 and Q1 are primary outputs and R is a primary input:
Derive a test sequence for detecting the fault G3 s-a-0. Verify your result by fault simulation using PROOFS.
Identify the SSFs in the circuit that prevent initialization. Then, determine whether these faults can be detected or not and under what conditions. Check whether these faults can be detected by HITEC or not and comment on the answer.
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BIST for delay fault testing.
Test vector compression and compaction techniques for deterministic testing of Combinational and sequential circuits.
Test pattern generation ad fault simulation for path delay faults.
High-level testability analysis and design for testability.
High-level automatic test pattern generation.
Core testing strategies and challenges.
Iddq testing.
Synthesis of testable Combinational and sequential circuits.
Testing and design for testability for asynchronous sequential circuits.
10. Board-level testing techniques.
11. Memory BIST techniques.
12.Test pattern generation and fault simulation for bridging faults.
13. Fault diagnosis in Combinational and sequential circuits.
14. Microprocessor testing techniques.
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Problem 4.8.Problem 4.10.Problem 4.12.Problem 4.17.
Given a manufacturing process with a certain yield Y and a test with certain fault coverage. Plot the Defect level (DL) curve as a function of the fault covera545COE 545 Digital System TestingSundayFeb 6Problem 4.8.Problem 4.10.Problem 4.12.Problem 4.17.Consider an n-input XOR gate:Determine the minimum number of SSFs faults that has to be targeted to detect all the SSFs in the gate.Determine the minimum number of test vectors required to detect all the SSFs.Let Z(x) be the function of a single-output combinational circuit N.
Give an example of a single stuck-at fault that changes the function from Z(x) to Z(x)`.
Show that if N is a single-output irredundant circuit, then none of the SSFs in N can change its function from Z(x) to Z(x)`.
Consider the circuit shown in Figure 4.23:Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence relation. Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence and dominance relations. Starting with the set of faults based on the checkpoint theorem (Theorem 4.2), perform fault collapsing using the equivalnce and dominance relations. Compare the set of collapsed faults to what you obtained in (ii).
Perform fault collapsing using HITEC. Compare the collapsed fault set to what you obtained in (ii) & (iii).
Consider the 2-bit counter shown below, where Q0 and Q1 are primary outpMondayJan. 31111.8353125omplement notations, assuming 16432132767 11111 0 00011
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Formula derived in class.
The Williams and Brown model: DL=(1-Y)(1-d) , where d is the defect coverage of the test. Assume that d is equal to the fault coverage as an approximauts and R is a primary input:
Derive a test sequence for detecting the fault G3 s-a-0. Verify your result by fault simulation using PROOFS.
Identify the SSFs in the circuit that prevent initialization. Then, determine whether these faults can be detected or not and under what conditions. Check whether these faults can be detected by HITEC or not and comment on the answer.
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Problem 4.8.Problem 4.10.Problem 4.12.Problem 4.17.
Given a manufacturing process with a certain yield Y and a test with certain fault coverage. Plot the Defect level (DL) curve as a function of the fault coverage for the cases when the yield Y=0.2, 0.4, 0.6 and 0.8 based on the following:
Formula derived in class.
The Williams and Brown model: DL=(1-Y)(1-d) , where d is the defect coverage of the test. Assume that d is equal to the fault coverage as an approximation. Compare the defect level curves in (i) and (ii).Consider an n-input XOR gate:Determine the minimum number of SSFs faults that has to be targeted to detect all the SSFs in the gate.Determine the minimum number of test vectors required to detect all the SSFs.Let Z(x) be the function of a single-output Combinational circuit N.
Give an example of a single stuck-at fault that changes the function from Z(x) to Z(x)`.
Show that if N is an irredundant circuit, then none of the SSFs in N can change its functio,KING FAHD UNIVERSITY OF PETROLEUM & MINERALSHassan R. BaradaITC/ACSQ..@P56CJOJQJo(()@P0.@
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Consider the circuit shown in Figure 4.23:Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence relation. Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence and dominance relations. Starting with the set of faults based on the checkpoint theorem (Theorem 4.2), perform fault collapsing using the equivalence and dominance relations. Compare the set of collapsed faults to what you obtained in (ii).
Perform fault collapsing using HITEC. Compare the collapsed fault set to what you obtained in (ii) & (iii).
Consider the 2-bit counter shown below, where Q0 and Q1 are primary outputs and R is a primary input:
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Give an example of a single stuck-at fault that changes the function from Z(x) to Z(x)`.
Show that if N is an irredundant circuit, then none of the SSFs in N can change its function from Z(x) to Z(x)`.
Consider the circuit shown in Figure 4.23:Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence relation. Starting with injecting faults on each line in the circuit, perform fault collapsing using fault equivalence and dominance relations. Starting with the set of faults based on the checkpoint theorem (Theorem 4.2), perform fault collapsing using the equivalence and dominance relations. Compare the set of collapsed faults to what you obtained in (ii).
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Identify the SSFs in the circuit that prevent initialization. Then, determine whether these faults can be detected or not and under what conditions. Check whether these faults can be detected by HITEC or not and comment on the answer.
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List of Proposed Projects
BIST for delay fault testing.
Test vector compression and compaction techniques for deterministic testing of Combinational and sequential circuits.
Test pattern generation ad fault simulation for path delay faults.
High-level testability analysis and design for testability.
High-level automatic test pattern generation.
Core testing strategies and challenges.
Iddq testing.
Synthesis of testable Combinational and sequential circuits.
Testing and design for testability for asynchronous sequential circuits.
Board-level testing techniques.
Memory BIST techniques.
Test pattern generation and fault simulation for bridging faults.
Fault diagnosis in Combinational and sequential circuits.
Microprocessor testing techniques.
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BIST for delay fault testing
Test vector compression and compaction techniques for deterministic testing of Combinational and sequential circuits.
Test pattern generation ad fault simulation for path delay faults.
High-level testability analysis and design for testability.
High level automatic test pattern generation.
Core testing strategies and challenges.
Iddq testing.
Synthesis of testable Combinational and sequential circuits.
Testing and design for testability for asynchronous sequential circuits.
Board-level testing techniques.
Memory BIST techniques.
Test pattern generation and fault simulation for bridging faults.
Fault diagnosis in Combinational and sequential circuits.
Microprocessor testing techniques.
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